Digital audio signal processor module

01

Check processing headroom and memory

Texas Instruments' TAS3204 datasheet describes an audio system-on-chip with a fully programmable 135 MHz digital audio processor, a 48-bit data path with a 76-bit accumulator, a single-cycle 28 × 48 multiplier and five simultaneous operations per clock cycle. Usable memory is 768 words of 48-bit data RAM, 1k words of 28-bit coefficient RAM, 2.5k words of program RAM, and 5.8k words of 24-bit delay memory, 122 ms at 48 kHz. [1]

The datasheet lists processing functions such as speaker equalisation and crossover, volume, bass and treble, mixing and splitting, delay compensation and dynamic range compression, with matrix decoding, stereo widening and virtual surround available as algorithms, and an embedded 8051 microprocessor for system control. [1]

Analog Devices' ADAU1701 SigmaDSP, a comparable single-chip audio system, lists a 28-/56-bit, 50 MIPS audio processor with a 28 × 28-bit multiplier and 56-bit accumulator for double-precision processing. Its processing blocks include equalisation, crossover, bass enhancement, multiband dynamics, delay compensation, speaker compensation and stereo image widening, configured graphically in SigmaStudio. Programs can self-boot from a serial EEPROM or be loaded by an external microcontroller, and parameters can be written back to the EEPROM at power-down. [2]

Editorial calculation: at 135 MHz and 48 kHz the core has about 135,000,000 ÷ 48,000 ≈ 2,800 clock cycles per sample; 122 ms of delay at an assumed 343 m/s speed of sound aligns loudspeakers up to about 42 m apart. Ask module suppliers how much of the processing and delay their default program already uses. [1]

Give the supplier the number of input and output channels, analogue and digital interfaces, sampling rate, processing blocks needed (EQ bands, crossovers, delay, dynamics, mixing), delay length, latency target, control (USB, Ethernet, RS-485, presets), software, power supply, connectors and housing.

02

Check converters, interfaces and programming

The TAS3204 integrates two 3:1 stereo analogue input multiplexers, four differential ADCs, for which the datasheet lists 102 dB dynamic range, and four differential DACs, listed at 105 dB, plus two synchronous serial audio inputs and two outputs (four channels each way) in 16-, 20- or 24-bit left-justified, right-justified or I2S formats. Sampling is 44.1 or 48 kHz in slave mode and 48 kHz in master mode, from a single 3.3 V supply with integrated regulators. [1]

It is programmed with TI's graphical drag-and-drop PurePath Studio environment, and code can be loaded over two I2C ports in slave or master mode. [1]

The ADAU1701 has two ADCs (100 dB SNR, −83 dB THD+N) and four DACs (104 dB SNR, −90 dB THD+N), an auxiliary ADC with a 4-input mux for analogue controls, and GPIOs. Its serial ports support I²S-compatible, left-justified, right-justified and TDM modes at sampling rates up to 192 kHz. A PLL generates the master clock from 64, 256, 384 or 512 × fS clocks, and it comes in a 48-lead LQFP. [2]

The I²S format named by both chips is defined in NXP's I²S bus specification: a continuous serial clock (SCK), word select (WS, 0 = left, 1 = right) and serial data (SD) sent in two's complement, MSB first, with WS changing one clock period before the MSB. [3]

Editorial note: a module's measured dynamic range also depends on its board layout, supply and analogue stages; ask for measured input-to-output dynamic range and THD+N of the finished module, not only the chip figures.

03

Matrices, speaker processors and DSP boards on supplier sites

Listings include digital audio matrices, speaker management processors, mini DSP boards, DSP amplifiers and networked audio interfaces.

04

Compare converter figures on the same metric and conditions

Cirrus Logic's product page for the CS47L63, a low-power audio DSP for earbud headphones and other portable audio devices, lists five converter figures for one chip: 120 dB SNR for headphone playback, 108 dB DAC dynamic range, −93 dB DAC THD+N, 99 dB SNR for a microphone input at 48 kHz and −87 dB ADC THD+N. It combines a programmable Halo Core DSP with fixed-function audio processors and sample-rate converters, takes up to four analogue or four PDM digital inputs, drives one DAC with a differential headphone output, and has two digital audio serial ports with multichannel operation at sample rates up to 192 kHz. [4]

Control is over I2C or SPI, power comes from 1.8 V and 1.2 V supplies, sleep current is 10 µA, and it comes in a 61-ball WLCSP with up to 12 GPIO pins. [4]

Editorial note: the same page gives 120 dB SNR for headphone playback and 108 dB for DAC dynamic range, a 12 dB gap (Editorial calculation: 120 − 108), so compare modules only on the same metric, weighting, sample rate and output, and ask each supplier for the measurement conditions behind every dB figure it quotes. [4]

05

Blocks inside an audio DSP module, from DSP core to clocking

06

Chip-level figures versus what the finished module must be measured for

07

Send the channel, processing and interface data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Channels: [inputs; outputs; analogue or digital]
Processing: [EQ; crossover; delay; dynamics; mixing]
Audio: [sampling rate; latency; dynamic range]
Control: [software; presets; network]
Hardware: [supply; connectors; size]
Quantity: [volume; customisation]

See manufacturer records Send an enquiry through CNFX