EtherCAT protocol processor: the on-the-fly frame processing unit inside an EtherCAT SubDevice controller chip, with its FMMUs, SyncManagers and process RAM
EtherCAT Processing Unit (EPU) · on-the-fly frame handling · ET1100, ET1200, LAN9252 and FPGA IP cores · forwarding delay, FMMU and SyncManager counts, process RAM, SPI or parallel host interface
In EtherCAT the protocol work is done in the devices on the line, not in the master. Each SubDevice controller (ESC) chip contains an EtherCAT Processing Unit that reads and writes its share of every passing frame while the bits are still moving through, increments the working counter, and hands the data to the local microcontroller through mapped memory. Beckhoff states that the master side needs no special hardware because standard Ethernet frames are used. This page is about that processing unit as it is bought: in an ASIC such as the Beckhoff ET1100 or ET1200, in Microchip's LAN9252 with integrated PHYs, or as an IP core in an FPGA. The figures that separate one device from another are the number of FMMUs and SyncManagers, the process RAM, the per-node delay and the interface to the host processor.
EtherCAT SubDevice (slave) controller ICs and FPGA IP cores considered through their EtherCAT Processing Unit: on-the-fly frame processing, port forwarding and processing delay, FMMU and SyncManager counts, process RAM and the process data interface to the local host. EtherCAT MainDevice (master) controllers and PC cards are covered on the EtherCAT controllers page; the Distributed Clocks time stamps, latch and SYNC functions of the same chips are covered on the Timestamp unit in an EtherCAT SubDevice controller page. Servo drives, I/O terminals, couplers and protocol gateways are outside this page.
CNFX editorial research · Sources checked October 19, 2026 · 3 sources
Frames are processed as they pass, not stored and forwarded
Beckhoff's ESC technology manual puts the EtherCAT Processing Unit (EPU) logically between port 0 and port 3. It receives, analyses and processes the EtherCAT data stream and coordinates access to the registers and memory that both the master and the local application address. Because the controller processes the frame in hardware, the manual says communication performance is independent of processor power. [1]
Frames are not stored inside the ESC: data is read and written as the bits pass, and the forwarding delay is set by the receive FIFO size and the EPU delay, with no transmit FIFO. The ET1100, ET1200, IP core and ESC20 support only Direct Mode addressing, so they hold no MAC or IP address and process EtherCAT frames with any address; for that reason unmanaged switches cannot be placed between these ESCs or between the master and the first SubDevice. [1]
Every datagram ends in a 16-bit working counter that the ESC increments in hardware: +1 for a successful read or write, and for a read-write command +1 for the read, +2 for the write and +3 for both. The master compares it with the value it expects. On a four-port device, a frame entering port 0 goes through the EPU first and then out through the other open ports in the order 3, 1, 2 before returning to port 0; ports that are closed or not implemented are passed over internally. [1]
Beckhoff warns that an ESC connected straight to an office network reflects every frame, including broadcasts, back into the network. Keep EtherCAT segments separate from plant IT Ethernet.
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Per-node delay through the processing unit on the ET1100
The ET1100 hardware description lists delays with FIFO size 7, for frames that go through the processing unit and for frames that are only forwarded alongside it. The average values are the ones Beckhoff says are used for Distributed Clocks calculations. [2]
Editorial calculation: a line of 10 SubDevices whose ET1100 controllers each use two MII ports adds 10 × 305 ns = 3.05 µs in the processing direction and 10 × 265 ns = 2.65 µs on the way back, 5.7 µs in total from the average figures. Cable propagation, PHY delays and the frame's own transmission time are not included and must be added for a cycle-time estimate. [2]
Beckhoff fixes EtherCAT transmission at 100 Mbit/s full duplex and states that an ESC has two to four ports, numbered 0 to 3. External PHYs connect through MII, RMII or RGMII; the EBUS physical layer is integrated in the ASICs. [1]
FMMUs map one continuous logical address range bit-wise onto physical ESC memory, so one datagram can address data held in different ESCs along the line; SyncManagers make the exchange with the local controller consistent and raise interrupts. Their number and the RAM size limit how many process data objects and mailboxes a device can run. [1]
In buffered mode, used for cyclic process data, a SyncManager physically occupies three buffers of the configured size: one for the producer, one for the consumer and one holding the last consistent data. Beckhoff's example configures 0x1000 with length 0x100 and shows the next usable RAM at 0x1300. [1] Editorial calculation: two buffered SyncManagers of 256 bytes each, one for outputs and one for inputs, therefore use 2 × 3 × 256 = 1,536 bytes, which exceeds the 1 KB of an ET1200 but fits in the 4 KB of a LAN9252 with room for mailboxes.
Microchip describes the same two modes for the LAN9252: in buffered mode the buffer always holds the latest data and older data is dropped if not read in time; in mailbox mode handshakes guarantee that no data is dropped. [3] Beckhoff gives the overall ESC address space as up to 64 KB, with registers and user memory in the first 4 KB and process memory from 0x1000 onwards. [1]
Host interface, supply and package on two shipping controllers
The process data interface (PDI) decides which processor can sit behind the chip. Beckhoff lists digital I/O, SPI slave, 8/16-bit microcontroller and on-chip bus PDIs depending on the ESC. [1]
The ET1100 supply figures exclude PDI and LED driver current, and Beckhoff recommends 3.3 V I/O because 5 V I/O through the internal LDO raises power dissipation; with an external 2.5 V core supply the 2 MII example falls to 42 mA core and 14 mA I/O (typ.). [2] Microchip limits the LAN9252 105 °C grade to the 64-QFN with an external regulator and 2.5 V (typ.) Ethernet magnetics. [3]
An ESC also needs a non-volatile memory for the EtherCAT Slave Information, which Beckhoff names as an I²C EEPROM, and an FPGA implementation needs a second one for its configuration. [1] The ET1100 needs a 25 MHz clock source with ±25 ppm initial accuracy and reports a start-up time of 340 ms until the PDI is operational. [2]
Item
Beckhoff ET1100
Microchip LAN9252
Host interfaces
32-bit digital I/O; SPI slave; 8/16-bit async or sync µController [2]
8/16-bit indexed or multiplexed host bus; SPI/SQI; digital I/O mode [3]
What to state when sourcing an EtherCAT SubDevice controller
Paste it into your enquiry below or into an email to a maker, then replace every bracket.
Ports: [2, 3 or 4; MII, RMII, RGMII or EBUS; PHYs integrated or external]
Process data: [bytes in and out; number of PDOs and mailboxes]
FMMUs and SyncManagers: [minimum count]
Host: [SPI or SQI clock; 8/16-bit bus; digital I/O only]
Distributed Clocks: [needed or not]
Supply and temperature: [3.3 V or 5 V I/O; grade]
Form: [ASIC; FPGA IP core; package]
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Compiled and source-reviewed by the CNFX editorial team.
Each manufacturer above links to the page on that company's own website where the product is listed, with the date we checked it. How we source and review
· Page last updated 19 October 2026
Buyer questions
Does an EtherCAT master need a special protocol chip?
Beckhoff states no: EtherCAT uses standard Ethernet frames, so a standard network controller works on the master side; processing is in the SubDevice controllers. [1]
How much delay does each EtherCAT node add?
For an ET1100, MII to MII through the processing unit averages 305 ns and forwarding alongside it 265 ns, with FIFO size 7. [2]
How many FMMUs and SyncManagers does a LAN9252 have?
Three FMMUs and four SyncManagers, with 4 KB of dual-port RAM. [3]
Sources and what still needs a direct check
Sources checked 2026-10-19. Beckhoff's EtherCAT Slave Controller technology manual (Section I) and ET1100 hardware description (Section III), and Microchip's LAN9252 data sheet.
