Editorial Technical Reference

Time-to-digital converter (TDC) IC

Time-to-digital converter ICs · Measurement range and modes, resolution and standard deviation, number of stops, reference clock and calibration, supply and current, host interface and package

A time-to-digital converter works like a picosecond stopwatch: it measures the interval between a start pulse and one or more stop pulses and outputs it as a number. Settle three things before choosing one: the interval range and resolution your time-of-flight measurement needs, the stop count, reference clock and calibration that set accuracy, and the supply current, interface, package and temperature range for the product.

Stand-alone time-to-digital converter ICs for ultrasonic flow meters, LiDAR and other time-of-flight ranging, and magnetostrictive position sensing. Ultrasonic analog front ends, complete flow meters and LiDAR sensors, time-interval counters as bench instruments and ADCs are outside this page; ADC chips have their own page.

CNFX editorial research · Sources checked October 12, 2026 · 4 sources

Time-to-Digital Converter (TDC) in a manufacturing environment
Representative product image. Confirm appearance and specifications with the manufacturer.

01

Set the measurement range, resolution and stops

TI's TDC7200 measures time between a START and up to five STOP pulses. Its electrical table specifies a 55 ps single-shot LSB (typ.), Mode 2 standard deviation of 35 ps at a measured interval of 1 µs and 50 ps at 100 µs (both typ.), and Mode 2 accuracy of 28 ps with an 8 MHz clock (typ.). The table conditions are ambient 25 °C, supply 3.3 V and ground 0 V unless otherwise noted. Mode 1 covers 12–500 ns; Mode 2 covers 250 ns–8 ms. [1]

START and STOP pulses must each be at least 10 ns wide. The TDC7200 coarse-counter and clock-counter overflow settings terminate intervals exceeding the selected limits. [1]

Editorial calculation: assuming ideal round-trip optical propagation at an approximate speed of 3 × 10⁸ m/s, with no front-end delay or offset, distance = speed × time ÷ 2. The 55 ps TDC7200 bin gives 3 × 10⁸ × 55 × 10⁻¹² ÷ 2 = 8.25 mm; the 500 ns Mode 1 upper limit gives 75 m. These are theoretical distance-bin and time-window equivalents, not manufacturer-published ranging performance or measured operating data; a time bin does not specify ranging accuracy. [1]

Give the supplier the shortest and longest interval to measure, the resolution and repeatability needed, the number of stop events, the reference clock available, the measurement rate and power budget, supply voltage, host interface, temperature range, package and quantity.

02

Check the reference clock, calibration, power and interface

The TDC7200 uses a 1–16 MHz external reference clock, nominally 8 MHz, and a self-calibrated time base. In its reference-clock discussion TI reports standard deviation of approximately 243 ps at 1 MHz and describes improved standard deviation at higher clock frequencies. The recommended supply is 2–3.6 V and operating temperature −40 to 85 °C. Its electrical table gives running current of 1.35 mA (typ., EN HIGH, TDC running) and shutdown current of 0.3 µA (typ.) / 2 µA (maximum, EN LOW), at ambient 25 °C and supply 3.3 V unless otherwise noted. [1]

TI separately lists 0.5 µA at 2 samples per second in the front-page features. Its autonomous multi-cycle averaging section describes taking measurements while the host sleeps. The feature current is not identified there as the consumption for a specified averaging-cycle count; obtain the current for the intended measurement schedule and configuration. [1]

The SPI timing table allows up to 20 MHz SCLK at 3.3 V supply. TI lists a 14-pin TSSOP body of 5.00 × 4.40 mm and the TDC1000 ultrasonic analog front end as a companion for flow-meter designs. [1]

03

Compare single, dual and flow-converter TDCs

The TDC7201 contains two TDCs. Each supports up to five STOPs per START; the individual measurement modes cover 12–2,000 ns in Mode 1 and 250 ns–8 ms in Mode 2. Combined operation is a separate arrangement covering 0.25 ns–8 ms. The electrical table gives a 55 ps LSB (typ.) and 35 ps standard deviation at a measured interval of 1 µs in Mode 2 (typ.). Running current is 2.7 mA (typ.), explicitly the sum of both TDCs, with both supplies at 3.3 V and ambient 25 °C unless otherwise noted. Recommended supply is 2–3.6 V and operating temperature −40 to +85 °C. [2]

The acam TDC-GP22 data sheet hosted by ScioSense describes an ultrasonic water/heat-meter converter. Its feature list, printed page 1-3 (PDF page 6), gives Mode 1 two-channel resolution of 90 ps (typ.) or 45 ps (typ.) with double resolution, and range “3.5 ns (0 ns) to 2.5 µs”. Its converter table, printed page 2-4 (PDF page 11), instead gives a 3.5 ns minimum and 2.4 µs maximum. Both upper limits are reproduced here: confirm the applicable range and zero-delay configuration with ScioSense before specifying the part. The table conditions are I/O and core supplies of 3.0 V and junction temperature 25 °C. [3]

The GP22 feature list specifies 20 ns pulse-pair resolution and four-fold multihit in Mode 1, with up to 500,000 measurements/s stated on the following page. Mode 2 has one channel, 700 ns–4 ms range and three-fold multihit. Its converter table marks the 90 ps, double-resolution 45 ps and Mode 2 quad-resolution 22 ps bins as typ. It includes first-wave detection with a programmable ±35 mV comparator and a fire generator with up to 127 pulses. The temperature unit supports two or four PT500/PT1000-or-higher sensors; its 0.08 µA figure is specifically for temperature measurement every 30 s. Core/I/O supply is 2.5–3.6 V, operating temperature −40 to +125 °C, with a four-wire SPI interface and QFN32 package. [3]

Editorial calculation: assuming the same ideal round-trip optical propagation at an approximate 3 × 10⁸ m/s, the GP22 feature-list ceiling of 2.5 µs converts to 375 m, while its converter-table ceiling of 2.4 µs converts to 360 m. These are hypothetical optical time-window equivalents, not ultrasonic distances, manufacturer-published ranging specifications or measured operating data. Confirm the conflicting source limits with ScioSense. [3]

04

Require interval-specific timing and current evidence

Request standard deviation and accuracy at the intended interval and reference clock, alongside STOP count and current for the selected acquisition schedule. TI reports these as separate parameters and conditions. [1]

05

Weigh an FPGA-based TDC when you need multiple channels

The IMSE-CNM team reports an Artix FPGA TDC using a tuned tapped delay line, a ones-and-zeros counter encoder and online calibration. With a 250 MHz clock, the study reports a 22.2 ps LSB, 26.04 ps single-shot precision, 8 ns dead time, 125 MSample/s readout and a 262.14 µs measurement range. Its 27.04 ps absolute-accuracy result is defined as maximum deviation of the calibration table from the ideal transfer function. These results belong to the described implementation and test setup. [4]

Source discrepancy: the abstract and results discussion/Table 2 give DNL [−0.953, 1.185] LSB and INL [−2.750, 1.238] LSB. Table 4 labels the same ranges in reverse: INL [−0.953, 1.185] LSB and DNL [−2.750, 1.238] LSB. Ask the authors to confirm the labels before using these figures. [4]

Table 3 lists 216 LUTs, 638 flip-flops and 2.50 block RAMs for one TDC channel, with 164 mW total power and 33 mW dynamic power. The authors explicitly obtain these data from the implementation report; the power figures are not presented as measured operating power. Their statement that the approach permits 400 TDC channels at 125 MSamples/s is a scalability claim, not a report of a tested full-channel installation. Their temperature experiment reports degradation in RMS precision over 30–75 °C for that setup. [4]

06

Fine timing, interval counters and calibration registers

BlockWhat it controlsFix in the order
Fine time measurementResolution. [1]ps LSB.
Coarse / clock countersLong intervals. [1]Mode; overflow.
CalibrationDrift. [1]Periods.
Start / stop inputsEvents. [1]Stops; width.
Averaging engineAutonomous repeated measurements with host sleep. [1]Cycle count and acquisition schedule.
SPI interfaceHost access. [1]SCLK.

07

TDC7200 mode limits and electrical test conditions

The values below refer to the TDC7200; electrical-table typ. values use ambient 25 °C and supply 3.3 V unless otherwise noted. [1]

FieldWhat it means and published valuesAsk the supplier for
Measurement Range12–500 ns (Mode 1); 250 ns–8 ms (Mode 2). [1]Min–max.
Resolution55 ps single-shot LSB (typ.). [1]ps.
AccuracyMode 2 accuracy 28 ps at 8 MHz (typ.); standard deviation 35 ps at 1 µs and 50 ps at 100 µs (typ.). [1]ps at interval.
Supply Voltage2–3.6 V. [1]V.
Power Consumption1.35 mA running (typ.); front-page feature 0.5 µA at 2 SPS, with no stated averaging-cycle count. [1]Current at rate.
Operating Temperature−40 to 85 °C. [1]Range.
Input FrequencyReference clock 1–16 MHz. [1]MHz.
Output InterfaceSPI, up to 20 MHz SCLK at 3.3 V supply. [1]Interface.
Package TypeTSSOP-14. [1]Package.
Operating HumidityBoard-level IC.Per system.
Ingress ProtectionBoard-level IC.N/A.

08

Send the timing, clock and power data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Interval: [min; max]
Resolution/SD: [ps]
Stops: [count]
Clock: [MHz]
Rate/power: [SPS; µA]
Supply/interface: [V; SPI]
Package/temp: [type; °C]
Quantity: [units]

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Find time-to-digital converter manufacturers

1 company lists this product among what they make. Company figures are quoted from each company's own website; every card states where the relationship came from.

Hangzhou Ruimeng Technology Co., Ltd.
TBC

Its website lists the MS10078 eight-channel time-to-digital converter.

Product scope checked 2026-10-16

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Buyer questions

What resolution does a TDC achieve?

The TDC7200 electrical table gives a 55 ps single-shot LSB (typ.) and Mode 2 standard deviation of 35 ps at a measured interval of 1 µs (typ.), under ambient 25 °C and supply 3.3 V unless otherwise noted. [1]

What range can a TDC measure?

The TDC7200 measures 12–500 ns in Mode 1 and 250 ns–8 ms in Mode 2. [1]

How does the reference clock affect a TDC?

TI reports approximately 243 ps standard deviation at a 1 MHz reference clock and describes improved standard deviation at higher reference-clock frequencies. Select the clock using the interval-specific requirements and clock specifications in the data sheet. [1]

Can a TDC run from a battery?

TI lists 0.5 µA at 2 samples per second as a TDC7200 feature and separately describes host sleep during autonomous multi-cycle averaging. The feature current is not tied to a specified averaging-cycle count; confirm consumption for the intended battery-powered acquisition schedule. [1]

Which TDC suits ultrasonic water meters?

ScioSense's TDC-GP22 is built for them, with first-wave detection, a fire-pulse generator and a PT1000 temperature unit; TI pairs its TDC7200 with the TDC1000 front end. [3] [1]

Can a time-to-digital converter be built inside an FPGA?

The IMSE-CNM study reports a 22.2 ps LSB and 26.04 ps single-shot precision in its Artix FPGA implementation. Table 3 lists 164 mW total and 33 mW dynamic power for its one-channel configuration, extracted from the implementation report rather than presented as measured operating power. [4]

Sources and what still needs a direct check

Sources checked 2026-10-12. TI data sheets define the IC electrical conditions; the acam GP22 data sheet supplies ultrasonic-converter modes, and the IMSE-CNM paper describes its FPGA implementation and test setup.

  1. Texas Instruments — TDC7200 time-to-digital converter datasheet (SNAS647D) ↗ Semiconductor datasheet Return to text ↑
  2. Texas Instruments — TDC7201 time-to-digital converter for time-of-flight applications datasheet (SNAS686) ↗ Semiconductor datasheet Return to text ↑
  3. ScioSense (acam) — TDC-GP22 ultrasonic flow converter datasheet ↗ Semiconductor datasheet Return to text ↑
  4. Parsakordasiabi, Vornicu, Rodríguez-Vázquez, Carmona-Galán (IMSE-CNM, CSIC–Universidad de Sevilla) — A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA, Sensors 21(1):308 (2021) ↗ Peer-reviewed paper Return to text ↑

Still to check yourself

  • Fix interval range.
  • Set resolution and SD.
  • Count stop events.
  • Choose reference clock.
  • Check current at rate.
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