Timestamp unit in an EtherCAT SubDevice controller: the Distributed Clocks latch that records input edges in network System Time
EtherCAT Distributed Clocks · The latch unit that stamps LATCH0/LATCH1 edges in 64-bit nanosecond System Time, the receive time stamps behind delay measurement, and the SYNC outputs that share its clock
In an EtherCAT network every SubDevice controller with Distributed Clocks keeps a local copy of one System Time. The timestamp unit is the part of that block that writes the System Time into registers when something happens: a rising or falling edge on a latch input, a frame arriving at a port, or a SyncManager buffer changing. Those stamps let a drive or I/O module say exactly when a probe switched or a mark passed, independent of when the next frame reaches the MainDevice. Choosing a controller or module therefore means checking which DC class it supports, how many latch inputs it exposes, and whether those pins are shared with the SYNC outputs.
The time-stamping functions of EtherCAT Distributed Clocks inside SubDevice controller ICs and FPGA IP cores: System Time format, receive time stamps for propagation delay measurement, the DC latch unit and its LATCH inputs, SyncManager event times, and the SYNC signal unit that shares the same clock. EtherCAT MainDevice controllers are covered on the EtherCAT controllers page; IEEE 1588 PTP camera synchronisation on the Vision camera array page; battery-backed calendar clocks on the Real-time clock (RTC) page; Ethernet PHYs on the Ethernet PHY chip page.
CNFX editorial research · Sources checked October 17, 2026 · 3 sources
Beckhoff's EtherCAT Slave Controller technology documentation (Section I) defines the System Time as starting on 1 January 2000 at 0:00, with a base unit of 1 ns, held as a 64-bit value; the lower 32 bits span about 4.2 s, and some ESCs implement only 32-bit DCs, compatible with the 64-bit ones. One DC-capable controller holds the reference clock (Beckhoff: "Typically, the Reference Clock is the first ESC with DC capability between master and all the slaves to be synchronized"); the others measure propagation delay with receive time stamps on their ports, compensate their offset, and continuously compensate drift by adjusting local clock speed. [1]
The same document sorts controllers into three DC classes: those with System Time and the time loop control unit (latch time stamping and SyncSignals optional), those supporting only propagation delay measurement with local clock and receive time stamps (mandatory for controllers with three or more ports), and two-port controllers without DC, treated as wire delay. It asks for ESC clock sources with an initial accuracy of 25 ppm or better. [1]
Editorial calculation: 2³² ns ≈ 4.29 s, which is the 4.2 s span Beckhoff gives for the lower 32 bits, and 2⁶⁴ ns ≈ 585 years. Two clocks each within 25 ppm can differ by up to 50 ppm, which over a 1 ms cycle is up to 50 ns of drift per cycle if left uncorrected; the 25 ppm figure is Beckhoff's, the cycle time an assumption. [1]
In a module data sheet, look for the DC class, 32- or 64-bit System Time, and the clock source accuracy; a controller limited to propagation delay measurement cannot stamp latch events.
02
LATCH0 and LATCH1: edge stamping, modes and registers
Beckhoff describes the DC Latch Unit as time-stamping both rising and falling edges of two external signals, LATCH0 and LATCH1, sampled at 100 MHz with an internal time stamp jitter of 11 ns; some controllers can also stamp SyncManager events. It runs in single-event mode, recording only the first rising and first falling edge until each is acknowledged by reading its time register, or in continuous mode. [1]
Microchip's LAN9252, a two-port EtherCAT SubDevice controller with an optional third MII port, includes a 64-bit distributed clock and brings out SYNC[1:0]/LATCH[1:0] as pins whose direction is configurable bit by bit, so each pin serves either as a SYNC output or a LATCH input; they stay high-impedance until the EEPROM is loaded. It runs from a 25 MHz crystal. [2]
Editorial calculation: with 11 ns of time stamp jitter, a mark on a conveyor moving at 2 m/s is located to within about 2 m/s × 11 ns = 22 nm from timing alone; the belt speed is an assumption, and sensor switching delay will dominate in practice. [1]
Register (ESC address)
What it holds
0x09A8 / 0x09A9
Latch0 / Latch1 control: single event or continuous [1]
System Time at Latch1 positive and negative edges [1]
0x09F0, 0x09F8, 0x09FC
Local time at EtherCAT buffer change, PDI buffer start and PDI buffer change events [1]
03
SYNC outputs from the same clock, and what the network delivers
The sync unit beside the latch unit generates SYNC0/SYNC1 from a start time and cycle time, updated at 100 MHz (10 ns) with 12 ns jitter against the local copy of System Time, according to Beckhoff's Section I. [1] The EtherCAT Technology Group states that clock calibration is entirely hardware-based and the resulting system jitter is significantly less than 1 µs, and that "Even jitter in the range of several microseconds does not diminish the accuracy of the Distributed Clocks", because outputs and input sampling are triggered by the local clock rather than by frame arrival. [3]
ETG's motion-control example is position capture: velocity is derived from position samples, so the samples must be taken at exactly equal intervals, which DC achieves by triggering them from the local clock rather than from frame arrival. [3] Where a pin is shared, as on the LAN9252, decide at board design which DC pins are latch inputs and which are SYNC outputs. [2]
04
Questions for a DC-capable SubDevice controller or module
Paste it into your enquiry below or into an email to a maker, then replace every bracket.
DC class: [System Time + latch / delay measurement only]
System Time: [64-bit or 32-bit]
Latch inputs: [how many; shared with SYNC?; single or continuous mode]
Sync outputs: [SYNC0/SYNC1; pulse length; interrupt use]
Clock: [crystal frequency; accuracy in ppm]
Host interface: [SPI, parallel or digital I/O mode]
Explore company information and manufacturing capabilities, then discuss the scope of your project with a relevant supplier.
Share this page
Compiled and source-reviewed by the CNFX editorial team.
Each manufacturer above links to the page on that company's own website where the product is listed, with the date we checked it. How we source and review
· Page last updated 18 October 2026
Buyer questions
What resolution does an EtherCAT latch time stamp have?
Beckhoff gives a System Time in 1 ns units, with latch inputs sampled at 100 MHz and 11 ns internal jitter. [1]
How many latch inputs does an EtherCAT SubDevice controller have?
Beckhoff's DC Latch Unit has two, LATCH0 and LATCH1; on Microchip's LAN9252 each shares a pin with a SYNC output. [1][2]
How accurate is EtherCAT Distributed Clocks synchronisation?
The EtherCAT Technology Group states system jitter significantly less than 1 µs. [3]
Sources and what still needs a direct check
Sources checked 2026-10-17. Beckhoff's ESC technology documentation and Microchip's LAN9252 datasheet describe the hardware; the EtherCAT Technology Group describes Distributed Clocks at system level.
