A fixed-priority encoder IC reports the highest-priority asserted input as an encoded address. Its combinational gate network resolves simultaneous requests according to the device’s fixed input order; status and enable signals define how the result is interpreted and cascaded.
Packaged fixed-priority encoder logic ICs with parallel request inputs and encoded address/status outputs. This is combinational priority logic, distinct from the clocked D-type storage devices on 6837. Programmable gate arrays, software interrupt controllers and rotary position encoders are outside this page.
CNFX editorial research · Sources checked October 18, 2026 · 3 sources
Read the encoded address with group and enable status
TI’s SN74HC148 encodes eight inputs into a three-line binary address, with active-low data inputs and outputs. The highest-order asserted input takes priority. EI and EO support cascaded stages. [1]
Its function table gives an all-high address both when no data input is active and when only the lowest-order input is active. GS and EO distinguish these states. An address word alone is therefore insufficient as a valid-request indication. [1]
TI warns that this combinational circuit can produce wrong addresses during input transitions, and that an enabling transition can cause a transient GS pulse when the data inputs are all high. Establish when the receiving logic samples the settled outputs. A static truth table is not a glitch-free event-capture guarantee. [1]
02
Check the supply and interface for the exact suffix
TI’s SDLS053B data sheet provides separate columns for its commercial and military-temperature LS parts. The SN74LS148 column specifies a recommended supply of 4.75–5.25 V and free-air temperature of 0–70°C. These are the commercial LS part’s conditions, not the military-temperature or HC-family columns. [2]
The same document separates the decimal-to-BCD encoder from the binary priority encoder and states active-low data for the types it covers. Match the full part number, input thresholds, output loading and pin functions; the shared priority-encoder label does not establish electrical interchangeability. [2]
For qualification-sensitive procurement, ST lists its M54HC148 as a radiation-hardened priority encoder in the ceramic-hermetic, ESCC-qualified product family and directs readers to the corresponding ESCC detailed specification. That specialised grade must be identified by its exact orderable part and qualification record; it is not a property of a generic commercial HC encoder. [3]
03
Define inactive requests and the sampling boundary
TI’s LS data sheet requires unused inputs to be held at a defined supply or ground level. Select the inactive level from the device’s function table; a floating request input is not a defined no-request state. [2]
Specify the request polarity and priority order, cascade connections, the interpretation of status outputs and the sampling point in the surrounding circuit. For asynchronous request sources, include their timing relationship in the system review. [1][2]
04
Identify the logic part and request interface
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Compiled and source-reviewed by the CNFX editorial team.
Each manufacturer above links to the page on that company's own website where the product is listed, with the date we checked it. How we source and review
· Page last updated 18 October 2026
Buyer questions
Does an all-high address necessarily mean there is no active request?
No. TI’s function table uses that address for both no active data and the lowest-priority active input; read GS and EO with the address. [1]
Is the priority encoder clocked storage?
TI identifies the HC device as combinational logic and warns of transient incorrect addresses during input changes. Its result needs to be sampled with the surrounding circuit’s timing defined. [1]
Sources and evidence scope
Sources checked 2026-10-18. TI’s explicitly revisioned CMOS and LS-family data sheets, plus ST’s specialised-grade product page. Operating conditions remain tied to the stated family and suffix.
