Arc-fault and ground-fault protection circuit assemblies

01

Name the fault and the measurement that exposes it

TI’s TIDA-010971 AC arc-detection reference design combines a PCB Rogowski sensor with filtered current channels, voltage sensing and a high-frequency log detector feeding an embedded processor. Its guide describes a laboratory evaluation platform. Treat its sensing architecture as a development example when specifying an offered protection assembly. [1]

Renesas’s residential AFCI design similarly examines line-current noise associated with arcing and runs Reality AI software on an MCU. Its published observation-window results describe the cited implementation. For a quotation, ask which loads, operating states and fault conditions formed the supplier’s validation set. [3]

Residual-current detection measures a different quantity. TI’s October 2026 TIDA-010237 revision uses a fluxgate sensor, driven magnetic-core excitation, filtering and comparator logic to detect AC and DC residual currents. Its system diagram separates this measurement path from the relay interrupting the power conductors. [2]

The current sensor, signal-processing IC and firmware must be specified as a matched signal path. Ask which conductors are measured, what frequency content or residual waveform is evaluated, and which power-conversion or load disturbances the algorithm is expected to tolerate. Identify sensor placement and supplied calibration data on the assembly drawing.

For a grid-connected inverter, mark the AC interface and any DC-side sensing separately. State whether the offered assembly provides arc detection, residual-current detection or both, and allocate the remaining protection functions in the inverter design. Keep the supplied hardware, firmware and tested operating modes under configuration control.

02

Time the fault decision and the physical interruption separately

TIDA-010237 revision B, revised October 2026, states a detection-to-response range of 3–50 ms and explicitly excludes relay delay. Its diagram shows a digital fault output to the controller and a separate power relay. Those boundaries matter when specifying the complete assembly’s disconnecting time. [2]

Request a timing definition that starts at the specified fault condition and ends at verified interruption of the relevant power path. Within that record, identify sensing/filtering time, algorithm or comparator decision, output-driver response and actuator/contact-opening delay. State the waveform, magnitude, supply and operating temperature used for the measurement.

The trip mechanism may sit outside the purchased detection PCB. Define the output’s electrical form, state during startup or loss of supply, latching behavior and reset ownership with the receiving controller or actuator. Request compatibility evidence for the actual driver, relay, contactor or breaker combination supplied.

Interrupting capacity belongs to the device that breaks the fault circuit and the conditions under which it is rated. A detection-board output rating, load-current sensing range or successful logic transition provides a different item of evidence. Identify the protective device, associated ratings and verified coordination in the assembled equipment file.

03

Show which part of the protection path each test exercises

Renesas publishes different arc-detection results for different observation windows in its reference implementation. A procurement test plan should identify the hardware, software, observation interval, test population and definition of a correct decision before comparing such results between offers. [3]

Document the supplied test circuit: test input, simulated condition, expected decision and observed endpoint. Distinguish a processor or comparator diagnostic from a test that includes the sensor and one that also verifies the actuator and opened contacts. State which test runs at startup, periodically or on manual command.

Agree the fault-detection cases and the normal-load cases that must remain energized, including startup, switching and power-converter modes relevant to the installation. Retain results for each offered configuration and any changed sensor or firmware build. Allocate the test facility and finished-equipment assessment to the responsible supplier or integrator.

At delivery, obtain the assembly schematic or controlled interface drawing, component list, firmware identity, calibration and functional-test records. Match the safety assessment or certificate to the exact finished equipment and claimed function. Record the response to a diagnostic failure and the conditions required for reset or replacement.

04

Assign each rating to the board, sensor, actuator or enclosure

05

Fault-detection assembly and complete shutdown-path specification

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Required functions: [AC arc detection, AC/DC residual-current detection, application and exact sensing location]
Signal chain: [sensor, measured conductors, front end, processor, firmware identity and calibration]
Fault behavior: [waveforms, thresholds/tolerances, decision criteria, normal-load immunity and operating envelope]
Shutdown interface: [output form, receiver/driver, actuator, interrupting-device identity, startup/loss-of-power states and reset]
Timing evidence: [fault inception, board response, actuator opening and verified power interruption under stated conditions]
Test coverage: [test circuit stimulus, sensor/logic/actuator coverage, diagnostics, normal-load cases and recorded results]
Delivery boundary: [parts/drawings, sensor and PCB, external trip hardware, enclosure, firmware, functional tests and finished-equipment assessment]

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