Crosspoint switch ICs for routing high-speed signals · Non-blocking N×N matrices, LVDS, CML and LVPECL inputs, data rate and jitter, propagation delay and skew, select and switch time, pin or SMBus control, pre-emphasis and equalisation, termination, ESD, supply current and packages
A crosspoint switch is an integrated circuit that connects any of its N inputs to any of its M outputs through a matrix of switches, so that signals — clocks, serial data, video — can be routed, duplicated (broadcast) or swapped under pin or software control. Ask three things first: how many inputs and outputs and which signal standard and data rate the paths carry, what jitter, skew and switching time the system budget allows, and how the switch will be controlled, terminated, powered and packaged.
Electronic crosspoint switch ICs for digital and high-speed differential signals (LVDS, CML, LVPECL inputs), including non-blocking N×N matrices with buffering, equalisation and pre-emphasis. Relay and RF switch matrices built from discrete switches, analogue video crosspoints, network packet switches and FPGA routing are outside this page except where compared; crossbar switch matrices and crosspoint switch arrays and elements are treated here as the same function.
01
TI's DS10CP154A is a 4×4 LVDS crosspoint switch for DC to 1.5 Gbps signal routing over FR-4 backplanes and balanced cables. Its fully differential, non-blocking architecture allows any input to connect to any output or outputs; a wide input common-mode range accepts LVDS, CML and LVPECL levels while outputs are LVDS; every input and output has an on-chip 100 Ω termination; loss-of-signal monitors can flag an open input such as a disconnected cable; and the LVDS pins are rated 8 kV HBM ESD. It runs from 3.0–3.6 V (3.3 V nominal) at −40 to 85 °C, in a 6 × 6 mm WQFN-40, and TI lists channel select, clock and data buffering and muxing, and SD/HD-SDI routers as uses. [1]
The SN65LVDS250 is a 4×4 non-blocking crosspoint in which each output driver has a 4:1 multiplexer so that any input can be routed to any output; TI rates it above 2.0 Gbps, with peak-to-peak jitter of 60 ps (typ.) at 2.0 Gbps and 110 ps (typ.) at 2.5 Gbps, 800 ps (typ.) propagation delay, inputs compatible with LVPECL, CML and LVDS, a single 3.3 V supply drawing 110 mA (typ.), a 38-pin TSSOP, −40 to 85 °C operation and ±3 kV HBM on all pins; the SN65LVDT250 version adds 110 Ω line termination. [3]
For lossy channels, TI's DS25CP104A extends the 4×4 LVDS crosspoint to 3.125 Gbps and adds four levels (off, low, medium, high) of transmit pre-emphasis and receive equalisation, set over SMBus (two levels by pins), to remove inter-symbol-interference jitter; TI lists SD/HD/3G-SDI routers, OC-48/STM-16, InfiniBand and FireWire as uses. [2]
Give the supplier the number of inputs and outputs, signal standards in and out (LVDS, CML, LVPECL), data rate or clock frequency, whether broadcast (one input to all outputs) is needed, channel length and loss, termination preference, control method, supply rail, temperature range, package and quantity.
02
For the DS10CP154A, TI gives maximum total jitter (PRBS-23) of 0.036 UI at 270 Mbps rising to 0.072 UI at 1.5 Gbps, deterministic jitter of 24–30 ps peak to peak maximum across 270 Mbps to 1.5 Gbps, and random jitter of 1.0–2.0 ps RMS maximum on clocks from 135 to 750 MHz. Differential propagation delay is 460–675 ps, channel-to-channel skew 40 ps (typ.) and 125 ps maximum, part-to-part skew 225 ps maximum, and rise and fall times 145–350 ps. [1] A select-pin change reaches the output in 8 ns (typ.) and 12 ns maximum; power-up takes 7–20 µs. [1]
Its supply current is 40 mA (typ.) with outputs powered down, 103 mA (typ.) and 125 mA maximum in 1:4 broadcast mode, and 115 mA (typ.) and 140 mA maximum as a 4:4 quad buffer; the SMBus interface runs at 10–100 kHz. [1] The SN65LVDS250 specifies select-to-output switch time of 1.2 ns nominal and 1.6 ns maximum. [1] [3]
Editorial calculation: at 1.5 Gbps one unit interval is 1/1.5 GHz ≈ 667 ps, so the DS10CP154A's 0.072 UI maximum total jitter is about 0.072 × 667 ≈ 48 ps; and at 3.3 V its 115 mA (typ.) quad-buffer current is about 3.3 × 0.115 ≈ 0.38 W (0.46 W at the 140 mA maximum). [1] Add the switch's jitter and skew to the transmitter, channel and receiver budget before choosing it. [1]
03
MACOM lists the M21605, M21601 and M21080 as 160x160, 120x120 and 80x80 asynchronous, fully nonblocking crosspoint switches, with each path running independently "at any data rate of up to 12.5 Gbps". Each input has a programmable equalizer compensating up to 27 dB of loss at 12.5 Gbps (6.25 GHz), and outputs offer up to 12 dB of post-tap and 5 dB of pre-tap de-emphasis. The M21605 is listed at 32 W power consumption in a 45x45mm package, with a single 1.8 V core and I/O supply, latency of less than 2 ns, four temperature sensors with programmable alarm, per-lane loss-of-signal detection and squelch, and 2-wire, 4-wire serial or 8-bit parallel configuration. [4]
The large matrix adds functions that the 4×4 data sheets on this page do not need: lane-by-lane power-down, loss-of-signal squelch, temperature alarms and JTAG boundary scan [4]. MACOM names serial digital video (SDI) and UHDTV/4K routers, DWDM switches and storage fabrics as applications. For a router design, ask for the equalisation and de-emphasis settings used to reach the stated data rate over your channel, and for the power at the number of lanes you will enable.
Power is the largest difference: the M21605 is listed at 32 W [4], against tens to about 140 mA at 3.3 V for TI's 4×4 LVDS parts [1]. TI's DS25CP104A shows pre-emphasis and equalisation at 3.125 Gbps [2]; at 12.5 Gbps MACOM specifies 27 dB of input equalisation, so ask how the switch is cooled and what loss your backplane traces present at 6.25 GHz.
Editorial calculation: 160 paths at 12.5 Gbps is 2,000 Gbps (2 Tbps) of switching capacity; 32 W over 160 channels is 0.2 W per channel; a TI 4×4 at 140 mA and 3.3 V draws about 0.46 W, or about 0.12 W per channel. [4] [1]
| Item | MACOM M21605 | TI DS25CP104A (already cited) | TI DS10CP154A (already cited) |
|---|---|---|---|
| Matrix | 160x160 (also 120x120, 80x80) | 4×4 | 4×4 |
| Data rate per path | Up to 12.5 Gbps | DC–3.125 Gbps | DC–1.5 Gbps |
| Input equalisation | Up to 27 dB at 6.25 GHz | Equalisation and pre-emphasis | — |
| Output de-emphasis | 12 dB post-tap, 5 dB pre-tap | Pre-emphasis | — |
| Power / supply | 32 W; 1.8 V core and I/O | — | 3.3 V nominal; 40–140 mA by mode |
| Package | 45x45mm | — | 6 × 6 mm WQFN-40 |
| Control | 2-wire, 4-wire serial or 8-bit parallel | SMBus | Pins or SMBus |
Values are from MACOM's M21605 product page; the data sheet was not reviewed.
04
No company carded on CNFX has been checked for crosspoint switch ICs yet; the Texas Instruments and MACOM parts on this page are cited as examples of what to specify, not as a supplier list.
05
The equaliser row applies to the DS25CP104A, which sets four levels of receive equalisation over SMBus; ask whether the part offered for your channel has one. [2]
| Block | Role | Fix in the order |
|---|---|---|
| Input receivers and termination | Accept LVDS, CML or LVPECL and terminate the line. [1] [3] | Input standards, termination value. |
| Switch matrix / output multiplexers | Connect any input to any output. [1] [3] | Size, non-blocking, broadcast. |
| Output drivers | Drive the outgoing lines. [1] [2] | Output standard, pre-emphasis. |
| Equaliser | Compensates channel loss at the input. [2] | EQ levels. |
| Control logic | Sets the connections by pins or SMBus. [1] [2] | Pin or bus control, LOS reporting. |
| ESD protection | Protects I/O pins. [1] [3] | HBM rating. |
| Package | Carries the die and pins. [1] [3] | WQFN or TSSOP, pin count. |
06
Insertion loss and isolation are the one row the cited data sheets leave blank for these digital switches; every other row has a TI or MACOM example.
| Field | What it means and published values | Ask the supplier for |
|---|---|---|
| Number of inputs/outputs | 4×4 non-blocking in three devices [1] [2] [3]; up to 160x160 in one family. [4] | Matrix size and broadcast support. |
| Bandwidth / data rate | DC–1.5 Gbps; above 2.0 Gbps; DC–3.125 Gbps [1] [3] [2]; up to 12.5 Gbps per path. [4] | Rate at your channel loss. |
| Jitter | 0.072 UI max total at 1.5 Gbps; 60 ps (typ.) at 2.0 Gbps. [1] [3] | Jitter at your rate and pattern. |
| Insertion loss / isolation (dB) | Ask: not stated in the reviewed sources for these digital switches. | Crosstalk and return loss data. |
| Switching time | 8–12 ns select time; 1.2–1.6 ns switch time. [1] [3] | Reconfiguration time. |
| Operating temperature (°C) | −40 to 85 °C. [1] [3] | Temperature grade. |
| Supply voltage (V) | 3.0–3.6 V, 3.3 V nominal. [1] [3] | Supply rails. |
| Power consumption (supply current) | 40–140 mA by mode; 110 mA (typ.). [1] [3] | Current in your mode. |
| Control interface | Pins or SMBus (10–100 kHz). [1] [2] | Control bus and address options. |
| Package type | 6 × 6 mm WQFN-40; 38-pin TSSOP. [1] [3] | Package and pinout. |
| ESD protection (kV) | ≥8 kV HBM on LVDS pins; ±3 kV HBM all pins. [1] [3] | ESD ratings. |
07
Paste it into your enquiry below or into an email to a maker, then replace every bracket.
Paths: [inputs; outputs; broadcast] Signals: [standard in and out; data rate or clock] Channel: [length; loss; EQ or pre-emphasis] Timing: [jitter budget; skew; switching time] Control and power: [pins or SMBus; supply; power budget] Package: [type; temperature; quantity]
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Any input can be connected to any output, or to more than one output at once, regardless of the other connections. [1] [3]
One LVDS crosspoint lists 8–12 ns from a select-pin change to the new signal at the output; another lists 1.2–1.6 ns. [1] [3]
On lossy backplane or cable channels at higher rates; one 3.125 Gbps crosspoint offers four levels of each to remove inter-symbol-interference jitter. [2]
MACOM lists 160x160, 120x120 and 80x80 asynchronous non-blocking crosspoint switches running each path at up to 12.5 Gbps, with 27 dB input equalisation; the 160x160 M21605 is listed at 32 W in a 45x45 mm package. [4]
Sources checked 2026-10-12. The TI data sheets describe one maker's LVDS crosspoint switches; jitter, timing and power for your paths must come from the device offered and your own channel analysis.
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