D-type flip-flop (logic IC)

01

Match the supply voltage and logic levels

TI's SN74LVC1G74 datasheet describes a single positive-edge-triggered D-type flip-flop with clear and preset, designed for 1.65–5.5 V supply: a low on preset or clear sets or resets the outputs regardless of other inputs; otherwise data meeting the setup time is transferred to the outputs on the rising clock edge, and triggering depends on a voltage level, not on clock rise time. Inputs accept up to 5.5 V, allowing down-translation to VCC. [1]

Input thresholds scale with supply — for example VIH 2 V and VIL 0.8 V at 3–3.6 V, and 0.7 × VCC and 0.3 × VCC at 4.5–5.5 V; maximum supply current is 10 µA, input leakage ±5 µA, output drive ±24 mA at 3.3 V, and Ioff circuitry disables the outputs when powered down to allow live insertion and partial power-down. ESD protection exceeds 2,000 V human-body model and 1,000 V charged-device model, and latch-up exceeds 100 mA per JESD 78. [1]

Nexperia's 74HC74 and 74HCT74 are dual positive-edge-triggered D flip-flops with individual data, clock, set and reset inputs and complementary outputs. The 74HC74 runs from 2.0 to 6.0 V with CMOS input levels — VIH at least 3.15 V and VIL no more than 1.35 V at 4.5 V — while the 74HCT74 runs from 4.5 to 5.5 V with TTL levels, VIH 2.0 V and VIL 0.8 V. Instead of 5.5 V-tolerant inputs, these parts have input clamp diodes that allow current-limiting resistors to interface inputs to voltages above VCC. [2]

The 74HC74 drives less current than the LVC parts: its output high level is at least 3.84 V at −4 mA and its output low level no more than 0.33 V at 4 mA with VCC = 4.5 V (−40 to 85 °C), and absolute output current is ±25 mA. Static supply current is up to 40 µA at 6.0 V (80 µA to 125 °C), and input leakage is ±1.0 µA. [2]

Editorial note: check that the driving circuit's output high voltage clears the flip-flop's VIH at its supply, and use input tolerance (LVC) or clamp diodes with a series resistor (HC) where a higher-voltage signal must be stepped down. [1] [2]

Give the supplier the supply voltage, input signal levels, clock frequency, setup and hold margins, need for preset/clear, number of bits, output load, partial-power-down needs, package, temperature range and quantity.

02

Check clock frequency, delay, setup and hold

The SN74LVC1G74 lists maximum clock frequency of 80 MHz at 1.8 V, 175 MHz at 2.5 and 3.3 V and 200 MHz at 5 V; clock-to-Q propagation delay of 2.2–5.9 ns at 3.3 V and 1.4–4.1 ns at 5 V (−40 to 85 °C); setup time of 1.3 ns and hold time of 1.2 ns at 3.3 V; and minimum clock pulse width of 2.7 ns at 3.3 V. Some packages are rated −40 to 125 °C, with slightly longer delays. [1]

It comes in small packages including the die-as-package NanoFree type and SSOP, and lists applications in servers, LED displays, network switches, telecom infrastructure, motor drivers and I/O expanders. [1]

The 74HC74 is far slower: at 4.5 V it lists clock-to-output delay of 17 ns (typ.) and 44 ns maximum, setup of 15 ns minimum, hold of 3 ns, clock pulse width of 20 ns and fmax of 24 MHz minimum and 69 MHz (typ.), with 50 pF load from −40 to 85 °C. [2] At 2.0 V the minimum fmax falls to 4.8 MHz and maximum delay rises to 220 ns. Its Schmitt-trigger clock input makes it tolerant of slower clock rise and fall times.

Set and reset add their own timing: on the 74HC74 the set or reset pulse must last at least 20 ns at 4.5 V, set or reset to output takes up to 50 ns, and a recovery time of 8 ns is needed after set or reset is released before the next clock edge. [2]

Editorial calculation: when one SN74LVC1G74 drives another at 3.3 V, the clock period must cover maximum delay plus setup — 5.9 + 1.3 = 7.2 ns, or about 139 MHz — below the 175 MHz fmax before any wiring or clock skew is added. [1]

Editorial calculation: for the 74HC74 at 4.5 V, delay plus setup is 44 + 15 = 59 ns, or about 16.9 MHz in a flip-flop-to-flip-flop path — below its 24 MHz minimum fmax. For hold, the SN74LVC1G79's minimum clock-to-Q delay of 1.7 ns at 3.3 V (30 or 50 pF) exceeds its 1 ns hold requirement by 0.7 ns, which is the clock-skew margin when one drives another. [2] [3]

03

Compare logic families and variants

TI's SN74LVC1G79 is a single positive-edge-triggered D flip-flop for 1.65 to 5.5 V without preset or clear. It lists a 160 MHz clock frequency at every supply from 1.8 to 5 V, minimum clock pulse duration of 2.5 ns, setup of 1.3 ns and hold of 1 ns at 3.3 V, and clock-to-Q delay of 1.7–5 ns at 3.3 V with 30 or 50 pF load (−40 to 85 °C) or up to 6 ns to 125 °C. Like the SN74LVC1G74 it has 5.5 V-tolerant inputs, ±24 mA drive at 3.3 V, 10 µA maximum supply current and Ioff partial power-down. [3]

Its packages run from a 2.90 × 2.80 mm SOT-23 to a 1.14 × 0.91 mm DSBGA. TI describes it as a data latch with low-voltage data retention: powered from 1.8 V, it holds the Q output through a supply glitch down to 1.5 V, and below 1.5 V retention is not guaranteed. Power dissipation capacitance is 27 pF at 3.3 V. [3]

The 74HC74 packs two flip-flops with set and reset in 14-pin SO14, TSSOP14, DHVQFN14 and 2 × 2 mm DHXQFN14 packages, all rated −40 to +125 °C. Its power dissipation capacitance is 24 pF, and the datasheet gives dynamic power as PD = CPD × VCC² × fi × N plus the sum of CL × VCC² × fo for the outputs. [2]

Editorial calculation: with the 74HC74's 24 pF CPD at 5 V and a 10 MHz clock on one input, the input term is 24 pF × 25 V² × 10 MHz = 6 mW, before output-load power is added. [2]

The same 74LVC1G74 function is also made by other suppliers under the same generic number, and the product pages show what differs. SG Micro Corp's 74LVC1G74 page describes a single positive-edge-triggered D flip-flop with clear and preset for a 1.65 V to 5.5 V supply, inputs that accept voltages above the supply, outputs that go high-impedance at VCC = 0 V with an Ioff circuit for partial power-down, +32 mA/−32 mA output current and a −40 to +125 °C operating range across its listed parts. Its ordering table lists VSSOP-8 (74LVC1G74XVS8G/TR) and XTDFN-1.4×1-8L packages, both rated MSL1 and marked as Pb-free, RoHS, REACH and Green. [4] Editorial note: SG Micro's page gives the 32 mA figure without the supply voltage it applies to, while TI quotes ±24 mA at 3.3 V for the SN74LVC1G74, so compare drive from both datasheets at the same VCC before treating the parts as drop-in equivalents, and check that the package footprints match. [4] [1]

04

Single or dual, preset and clear, and temperature grade to ask a flip-flop supplier

3PEAK, the one card shown, lists the T74L1G74 single D-type flip-flop with set and reset.

Ask each supplier for the datasheet timing at your supply and temperature, input thresholds and tolerance, output drive and the package options. [1]

Ask whether the part number is single or dual, with or without preset and clear, and which temperature grade each package carries: the 74HC74 is specified from −40 to +85 °C and −40 to +125 °C, and its ESD protection exceeds 2,000 V HBM and 1,000 V CDM with latch-up above 100 mA per JESD 78. [2]

05

D and clock, preset and clear, outputs, input stage, Ioff and Schmitt clock

The first five rows come from TI's SN74LVC1G74 datasheet; the Schmitt-trigger clock and input clamp diode rows are features of Nexperia's 74HC74.

06

Supply, delay, fmax, setup and hold, thresholds and leakage for LVC and HC flip-flops

Each value names the part it comes from, because the LVC figures are quoted at 3.3 V and the HC figures at 4.5 V.

07

Send the supply, timing and package data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Supply: [V]
Input levels: [V; tolerant?]
Clock: [MHz]
Timing: [tpd; setup; hold]
Functions: [preset; clear; bits]
Output load: [mA]
Package/temp: [type; °C]
Quantity: [units]

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