Electronic delay lines for timing and RF signals · programmable logic delay lines and digitally controlled RF delay lines, step size, delay range, linearity, frequency range, insertion loss, switching time and programming interface
An electronic delay line holds back an electrical signal by a set time so that clocks, pulses or RF signals line up with the rest of a system. This page covers two forms: digital programmable delay lines, which delay logic edges, and RF delay lines, which delay a microwave signal over a frequency band. Ask three things first: what signal it must carry (logic edges or an RF band), what delay range and step size you need, and how the delay will be set.
Electronic delay lines that delay electrical signals: programmable logic delay chips and digitally controlled RF and microwave delay lines. Optical fibre delay lines and software delays are outside this page.
01
Colby Instruments' product comparison chart sets out three technologies for programmable delay line instruments. Its XT-100 uses trombone (or trombone plus relay) technology over 0–18.0 GHz with a 0.25 ps minimum step and maximum delay options from 625 ps to 100.0 ns. The XR-100 uses relays over 0–18.0 GHz with 5 ps, 10 ps or 1 ns steps and delays up to 50.95 ns, 101.91 ns or 200.0 ns. The XS-100 uses solid-state PIN diodes over 100 MHz to 3.5 GHz with 1 ps or 5 ps steps and 5.12 ns or 10.23 ns maximum delay; Colby says the XS series gives "the fastest switching speeds within a limited signal bandwidth". [3]
The chart lists the dual-channel XT-200 at 312.5 or 625.0 ps per channel, rates the microwave relays in the XT-100 and XR-100 at "5m MTBF", and recommends a service interval of 500,000 operations or 1 year for the trombone units and 1 year for the XR-100. Every model has Ethernet TCP/IP, serial RS-232 and a web browser interface; an external trigger is listed for the XT-100-OEM, XR-100 and XS-100 but not for the XT-100 or XT-200. [3]
Editorial calculation: 625 ps in 0.25 ps steps gives 625 / 0.25 = 2,500 settings. Ask the supplier for the switching time of the exact configuration, the insertion loss at your frequency and the relay or trombone service life. [3]
02
The DS1023 data sheet describes an 8-bit programmable delay line that can also be set up as a pulse-width modulator or a free-running oscillator. In normal mode the output copies the input's logic state after a delay set by eight program inputs, which can be loaded in parallel or serially. A programmed value of zero still gives a non-zero step-zero delay, so an on-chip reference output, trimmed slightly longer than step zero, is provided to offset it. The device can delay clocks by a full period or more, so clock phase can be varied over 0–360 degrees, and its monotonicity is guaranteed. [1]
Editorial calculation: in each version the maximum delay is 255 times the step size (for example 255 × 0.25 ns = 63.75 ns), which matches 8-bit programming. The data sheet gives a single 5 V supply, 16-pin DIP or SOIC packages and an operating range of 0 to 70 °C; ask the supplier for current equivalents. [1]
| Version | Step size | Maximum delay | Maximum input frequency |
|---|---|---|---|
| DS1023-25 | 0.25 ns | 63.75 ns | 25 MHz [1] |
| DS1023-50 | 0.5 ns | 127.5 ns | 25 MHz [1] |
| DS1023-100 | 1 ns | 255 ns | 25 MHz [1] |
| DS1023-200 | 2 ns | 510 ns | 25 MHz [1] |
| DS1023-500 | 5 ns | 1,275 ns | 10 MHz [1] |
Give the supplier the signal type (logic family or RF band), the delay range and step size, the accuracy or linearity needed, the maximum input frequency or bandwidth, insertion loss and VSWR limits for RF, the switching time, the control interface, the supply voltage, the package or connectors, and the temperature range.
03
A 2021 paper from Palacký University, Olomouc (Mazin, Stejskal, Dudka and Ježek; arXiv:2105.09183; related journal DOI 10.1063/5.0056828) reports a non-blocking programmable delay line built from logic primitives in a Cyclone IV EP4CE6E22C6N FPGA. It chains 24 stages, each a block of look-up tables (LUTs) with a 2-to-1 multiplexer bypass, set by a 24-bit control word. From calibrated stage delays the authors selected 160 × 10³ delay values with a target granularity of 10 ± 5 ps, covering 23 ns to 1635 ns. [4]
The paper sets the dead time against single-photon avalanche diodes, which it lists at 50–300 ps jitter and 10–50 ns dead time, and states that 22.5 ns of dead time corresponds to a bandwidth of 20 MHz or more across the delay range. The authors attribute the granularity spread to the 20 ps inter-channel jitter of their oscilloscope during calibration. [4]
Editorial calculation: the jitter formula at the 1635 ns maximum gives 4.726 + 0.098 × 1635 ≈ 165 ps, matching the reported upper value; a 1612 ns span (1635 − 23) in 10 ps steps would need 161,200 settings, close to the 160 × 10³ values the authors loaded. [4]
| Parameter | Measured or stated value |
|---|---|
| Delay range | 23 ns to 1635 ns [4] |
| Target granularity | 10 ± 5 ps; measured steps stayed within ± 100 ps [4] |
| Zero-delay path | 18.808 ns at 21.5 ± 0.2 °C [4] |
| Timing jitter | 7 ps to 165 ps; σ[ps] = 4.726 + 0.098 τ[ns] [4] |
| Dead time | 4 ns to 22.5 ns (22.5 ns is 1.4% of the maximum delay) [4] |
| Temperature coefficient | 0.2 ps/K per LUT, measured from 30 °C to 60 °C [4] |
| Input | SMA, 50 Ω terminated; -0.2 V to +5.1 V allowed, 0 V to +3.3 V recommended [4] |
When comparing delay lines, ask for jitter as a function of the delay setting, the dead time or maximum repetition rate, the zero-delay (insertion) delay and the delay drift per kelvin, not only the step size. [4]
04
Qualwave, a microwave component maker, lists digitally controlled delay lines for radar, communication systems and laboratory test at frequencies up to 18 GHz. It states delay steps as small as 1.25 ps and total ranges that can reach 25 ns or more. Its listed model QDDL-100-18000-78.75-1.25 covers 0.1–18 GHz with a 1.25–78.75 ps delay range in 1.25 ps steps. Typical accuracy is ±4 ps, insertion loss 10 dB and VSWR 1.8, with a maximum switching time of 25 ns and a typical maximum power of 24 dBm. [2]
Editorial calculation: 1.25 to 78.75 ps in 1.25 ps steps gives 63 delay values. Ask the maker how the delay is controlled and how many control bits it uses.
05
This is a functional reference built from the sources cited; it is not one maker's specification.
| Function | Role | Fix in the order |
|---|---|---|
| Delay elements | Set delay in steps (0.25–5 ns logic; 1.25 ps RF). [1] [2] | Step size; range. |
| Program register | Parallel or serial setting of the delay. [1] | Interface; latch. |
| Reference output | Offsets the step-zero delay. [1] | Needed or not. |
| RF path | Carries the signal over the band with insertion loss and VSWR limits. [2] | Band; loss; VSWR; power. |
| Switching | Time to change the delay setting. [2] | Switching time. |
06
A delay line quotation needs values for your signal. The table explains each field, gives published values where a reviewed source states them, and says what to ask the supplier for.
| Field | What it means and published values | Ask the supplier for |
|---|---|---|
| Signal | Logic edges up to 25 MHz input; RF 0.1–18 GHz. [1] [2] | Signal type and band. |
| Delay range | Examples: up to 1,275 ns (logic); 1.25–78.75 ps (RF model). [1] [2] | Range for your system. |
| Step size | Examples: 0.25–5 ns; 1.25 ps. [1] [2] | Step and accuracy. |
| RF losses | Example: 10 dB insertion loss; VSWR 1.8 (typical). [2] | Loss and VSWR over band. |
| Control | Parallel or serial (logic); switching time 25 ns max (RF). [1] [2] | Interface; switching time. |
| Environment | Example: 0–70 °C operating. [1] | Temperature range. |
07
Paste it into your enquiry below or into an email to a maker, then replace every bracket.
Signal: [logic family and frequency; or RF band] Delay: [range; step; accuracy] RF: [insertion loss; VSWR; power] Control: [parallel; serial; switching time] Package: [SMD/DIP; connectors] Environment: [temperature; supply]
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Lists digitally controlled RF delay lines up to 18 GHz, with model specifications.
Product scope checked 2026-10-11
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The DS1023 reproduces the input's logic state at its output after a delay set by eight program inputs, in steps of 0.25 to 5 ns depending on version. [1]
Qualwave lists digitally controlled delay lines with steps as small as 1.25 ps up to 18 GHz. [2]
No. The DS1023 has a non-zero step-zero delay and provides a reference output to offset it. [1]
Colby Instruments' comparison chart says its PIN-diode XS series gives the fastest switching, over 100 MHz to 3.5 GHz, while its trombone XT series offers 0.25 ps steps up to 18.0 GHz. [3]
In the FPGA delay line reported by Mazin et al. (2021), jitter rose linearly from 7 ps to 165 ps over a 23–1635 ns delay range set in 10 ps steps. [4]
Sources checked 2026-10-11. The DS1023 data sheet (Maxim; archived copy from analog.com), Qualwave's product page and Colby Instruments' comparison chart describe their own devices; their figures are examples, not limits. The Palacký University paper by Mazin et al. (2021) gives measured values for one FPGA-based delay line.
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