Digital datapaths · shared-select bus routing
A shared-select digital multiplexer routes a parallel logic word from the selected input bank to its outputs. The enable input controls the entire output bank; its inactive state must match the receiving circuit’s needs.
Shared-select quad digital multiplexers that route one of two parallel logic words to a shared output bank, for combinational selection in processor datapaths and control circuits. Custom chip design is covered on the Application-specific integrated circuits (ASICs) page (3590); hardware contact conditioning is covered on Debounce circuit (6480). Analog signal switches, optical multiplexers and packet switches are outside this page.
01
TI’s SN74LVC157A contains four non-inverting 2-to-1 selectors controlled together. With the shared strobe G LOW, a 4-bit word from the selected source appears at the four outputs. The function table selects the A inputs when A/B is LOW and the B inputs when it is HIGH. [1]
This is parallel word selection: corresponding bits share the same selection decision. Specify which operand, register bank or control word each input bank carries, and check the receiving logic’s timing against the chosen device’s data and select paths. [1]
02
The MC74HC157A function table in onsemi’s May 2011 Rev. 10 data sheet sets every Y output LOW when Output Enable is HIGH, regardless of Select. When Output Enable is LOW, Select chooses the A or B input word. This is a driven logic state, not a high-impedance bus release. [3]
TI’s HC/HCT data sheet distinguishes the non-inverting 157 types, whose disabled outputs are LOW, from the inverting 158 types, whose disabled outputs are HIGH. Check both polarity and disable behaviour when substituting a part; a shared package or related name does not establish the same truth table. [2]
03
For SN74LVC157A, input tolerance above the supply does not raise the output rail: its recommended output-voltage range remains bounded by VCC. Match the selected device’s input thresholds to the driving logic and its output levels to the receiver. TI also requires unused inputs to be held at VCC or GND. [1]
| Named device or family | Published operating conditions |
|---|---|
| TI SN74LVC157A | Operating VCC 1.65–3.6 V; input voltage 0–5.5 V and output voltage 0–VCC in the recommended operating conditions. At VCC 2.7–3.6 V, VIH minimum is 2 V and VIL maximum is 0.8 V. [1] |
| TI HC types in SCHS153C | Operating supply 2–6 V. [2] |
| TI HCT types in SCHS153C | Operating supply 4.5–5.5 V; LSTTL-compatible input limits VIH minimum 2 V and VIL maximum 0.8 V. [2] |
Provide the input-bank mapping, required enable state, logic rails, receiver thresholds, load capacitance, timing budget and package. Obtain switching limits for that supply, load and temperature from the exact ordering-code data sheet.
04
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Input banks: [signal mapping and driving logic] Control: [select source; enable state] Electrical: [supply; input levels; receiver; load] Timing: [data/select budget; temperature] Part: [ordering code; package; qualification]
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The cited SN74LVC157A and MC74HC157A truth tables force the outputs LOW when the shared strobe or Output Enable input is HIGH. [1] [3]
The cited TI data sheet lists HC operation at 2–6 V and HCT operation at 4.5–5.5 V. Select using the actual rail and logic thresholds. [2]
Sources checked 2026-10-16. TI documents the LVC and HC/HCT families separately. The archived onsemi data sheet is used for the MC74HC157A truth table, with its revision stated.
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