Serializer/deserializer (SerDes) ICs · Line rate vs payload with encoding, parallel or CSI-2 interface width, media and reach, back channel, power, qualification and package
A SerDes (serializer/deserializer) converts wide parallel or multi-lane data into a fast serial stream for transmission over a board trace, cable or fibre, and converts it back at the far end, cutting the number of wires and connector pins. Settle three things before choosing one: the payload bandwidth and the line rate it needs after encoding, the interface on each side and the media and reach, and the control channel, power, qualification grade and package.
Stand-alone serializer, deserializer and SerDes transceiver ICs, including camera and display link serializers. SerDes blocks inside FPGAs and switches, retimers and redrivers, optical transceiver modules and Ethernet PHYs are outside this page; clock and data recovery retimers have their own page.
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01
TI's TLK2711-SP is a 1.6–2.5 Gbps serializer/deserializer for point-to-point baseband transmission over controlled-impedance media of about 50 Ω — PCB, copper cable or fibre via optical converters. It has a 16-bit parallel TTL-compatible data interface, on-chip 8-bit/10-bit encoding and decoding with comma detection, an on-chip PLL that synthesises the serial clock from a low-speed reference, programmable output pre-emphasis, loss-of-signal detection and integrated 50 Ω receive termination, providing up to 2 Gbps of data bandwidth. TI notes it can replace parallel buses to reduce traces and connector pins, and that rate and distance depend on media attenuation and noise. [1]
TI's DS90UB953-Q1 is an FPD-Link III serializer with a MIPI D-PHY v1.2 / CSI-2 v1.3 input of up to four data lanes at 832 Mbps per lane and up to four virtual channels, sending a 4.16 Gbps forward channel to a companion deserializer, for 2.3 MP 60 fps and 4 MP 30 fps imagers, satellite radar, lidar and time-of-flight sensors. [2]
Editorial calculation: with 8b/10b coding, a 2.5 Gbps line carries 2.5 × 8 ÷ 10 = 2 Gbps of data, which a 16-bit interface delivers at 125 MHz; four CSI-2 lanes at 832 Mbps total 3.33 Gbps, within the 4.16 Gbps forward link. [1] [2]
FPD-Link III is TI's own link; the MIPI Alliance publishes a standard alternative, MIPI A-PHY, a long-reach SerDes physical layer for cameras, sensors and displays with an asymmetric link in point-to-point or daisy-chain topology, up to 15 m reach, and high-speed data, control data and optional power on one cable. Versions 1.0 and 1.1 define five downlink gears of 2, 4, 8, 12 and 16 Gbps and two uplink gears of 100 and 200 Mbps; version 2.0 doubles the baud rate from 4 to 8 GBaud, adding 24 and 32 Gbps downlink gears and a 1.6 Gbps uplink gear. MIPI states a packet error rate of 10^-19, and A-PHY v1.0 was adopted as IEEE 2977-2021 in June 2021. [4]
Editorial note: the DS90UB953-Q1's 4.16 Gbps forward channel sits between the A-PHY 4 Gbps and 8 Gbps downlink gears; the gear an A-PHY camera link needs follows from the CSI-2 payload (up to 3.33 Gbps for four 832 Mbps lanes, per the calculation above) plus the link overhead the device maker states. [2] [4]
Give the supplier the payload bandwidth and data format, parallel width or CSI-2/LVDS lane count, encoding, line rate, media (PCB, coax, STP, fibre) and length, BER target, back-channel or control needs (I²C, GPIO), power over cable, reference clock, supply rails and power budget, qualification grade (commercial, automotive AEC-Q100, space), temperature range, package and quantity.
02
The DS90UB953-Q1 supports single-ended coaxial or shielded-twisted-pair cable with power over coax, an ultra-low-latency 50 Mbps bidirectional control channel carrying I²C and GPIO from the ECU to the sensor, precision multi-camera clocking and synchronisation, and diagnostics including CRC data protection, sensor data integrity checks, I²C write protection, voltage and temperature measurement and line-fault detection. It is AEC-Q100 Grade 2 (−40 to +105 °C), ISO 10605 and IEC 61000-4-2 ESD compliant, runs from a single 1.8 V supply at 0.28 W typical, and comes in a 5 × 5 mm VQFN. [2]
The TLK2711-SP lists power under 500 mW, hot-plug protection, 3 V tolerance on its parallel inputs, a military temperature range of −55 to 125 °C case and a 68-pin ceramic quad flat pack. [1]
Editorial note: pair a serializer with a deserializer the maker lists as compatible; TI lists the DS90UB953-Q1's compatible FPD-Link deserializers by part number. [2]
MIPI A-PHY carries CSI-2, DSI-2 and VESA DisplayPort/eDP through protocol adaptation layers, with adaptation layers for I²C, GPIO, Ethernet and SPI control channels. Version 1.1 added Star Quad dual-differential-pair cable for two A-PHY ports on one cable, raising total downlink from 16 to 32 Gbps, plus optional PAM4 coding on gears G1 and G2. [4]
On the receive side, TI's DS90UB954-Q1 is a dual deserializer hub that aggregates one or two FPD-Link III sensors into a MIPI CSI-2 output of 1, 2, 3 or 4 data lanes at 400 Mbps, 800 Mbps, 1.5 Gbps or 1.6 Gbps per lane, with four virtual channels, ECC and CRC generation and a 2×2 output replication mode. It receives over 50 Ω single-ended coax or 100 Ω differential shielded twisted pair, with an adaptive receive equaliser that compensates for cable loss, a separate bidirectional control channel per link carrying I²C (fast-mode plus up to 1 Mbps) and GPIO, and line-fault detection. TI lists it as compatible with the DS90UB935-Q1, DS90UB953-Q1, DS90UB933-Q1 and DS90UB913A-Q1 serializers; it is AEC-Q100 temperature grade 2 (−40 to +105 °C ambient) in a 48-pin 7 × 7 mm VQFN. [3]
Editorial calculation: four CSI-2 output lanes at 1.6 Gbps give the DS90UB954-Q1 up to 4 × 1.6 = 6.4 Gbps of output lane capacity for the one or two sensors it aggregates; confirm the per-lane rate your processor accepts. [3]
03
The companies in the manufacturer list below show this product on their own websites. Confirm the legal seller, factory and scope for your order.
Ask any supplier for link-budget data at your cable length, the compatible partner device and the qualification report. [1] [2]
04
This is a functional reference built from the sources cited; it is not one maker's specification.
| Block | What it controls | Fix in the order |
|---|---|---|
| Parallel / CSI-2 interface | Input width and format. [1] [2] | Width; lanes. |
| Encoder (8b/10b) | Overhead; DC balance. [1] | Coding. |
| PLL clock synthesis | Line rate from reference. [1] | Reference. |
| Output driver and pre-emphasis | Reach over media; adaptive receive EQ. [1] [3] | Levels. |
| Back channel | Control and GPIO; A-PHY uplink gears 100 Mbps, 200 Mbps, 1.6 Gbps. [2] [4] | Rate; protocol. |
| Diagnostics and protection | CRC; line fault; ESD. [2] | Features. |
05
A SerDes quotation needs values for your link. The table explains each field, gives published values where a reviewed source states them, and says what to obtain from the supplier.
| Field | What it means and published values | Ask the supplier for |
|---|---|---|
| Data Rate | 1.6–2.5 Gbps; 4.16 Gbps; A-PHY downlink gears 2–16 Gbps (v1.x) and 24/32 Gbps (v2.0). [1] [2] [4] | Line and payload rate. |
| Number of Lanes | 16-bit parallel; 4 CSI-2 lanes in; 1–4 CSI-2 lanes out. [1] [2] [3] | Width. |
| Supply Voltage | 1.8 V single. [2] | Rails. |
| Power Consumption | <500 mW; 0.28 W typ. [1] [2] | At your rate. |
| Operating Temperature | −55 to 125 °C case; −40 to 105 °C. [1] [2] | Range. |
| ESD Tolerance | ISO 10605, IEC 61000-4-2. [2] | Levels. |
| Package Type | 68-pin CQFP; 5 × 5 mm VQFN; 48-pin 7 × 7 mm VQFN. [1] [2] [3] | Package. |
| Jitter (RMS) | Transmit jitter. | ps. |
| Bit Error Rate | Link error rate; A-PHY states a packet error rate of 10^-19. [4] | Target; test. |
| Input/Output Logic Level | TTL parallel; 3 V tolerant. [1] | Levels. |
| Latency | Ultra-low latency control channel. [2] | ns. |
| Humidity (Non-condensing) | Environment. | % RH. |
06
Paste it into your enquiry below or into an email to a maker, then replace every bracket.
Payload: [Gbps; format] Interface: [parallel width; CSI-2 lanes] Link: [media; length; connector] Control: [I²C; GPIO; back-channel rate] Power: [PoC; rails; W] Qualification: [commercial; AEC-Q100; space] Package/temperature: [package; range] Quantity: [units]
These companies list serdes on their own websites.
Its website has a product page for serdes.
Product scope checked 2026-10-12
Explore company information and manufacturing capabilities, then discuss the scope of your project with a relevant supplier.
Encoding overhead; TI's TLK2711-SP uses 8b/10b, so 2.5 Gbps carries up to 2 Gbps of data. [1]
Yes; TI's DS90UB953-Q1 sends CSI-2 camera data at 4.16 Gbps over a single coax with power over coax. [2]
A reverse link for control; the DS90UB953-Q1 has a 50 Mbps bidirectional I²C and GPIO channel. [2]
TI says it reduces the number of traces, connector pins and transmit/receive terminals. [1]
It receives two or more serial links and merges them; TI's DS90UB954-Q1 aggregates one or two FPD-Link III sensors into a CSI-2 output of up to four lanes at up to 1.6 Gbps each. [3]
Yes; MIPI A-PHY, adopted as IEEE 2977-2021 in its v1.0 form, reaches up to 15 m with downlink gears from 2 to 16 Gbps, extended to 24 and 32 Gbps in v2.0. [4]
Sources checked 2026-10-11. Texas Instruments publishes datasheets for the TLK2711-SP SerDes transceiver and DS90UB953-Q1 camera serializer, and a product page for the DS90UB954-Q1 deserializer hub; the MIPI Alliance publishes the overview of its A-PHY long-reach automotive SerDes physical-layer specification.
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