Phase-locked loop (PLL) synthesizer

01

Set the output range and phase-noise budget

TI's LMX2594 datasheet describes a wideband PLL synthesizer that generates any frequency from 10 MHz to 15 GHz without an internal doubler, with −110 dBc/Hz phase noise at 100 kHz offset on a 15 GHz carrier and 45 fs rms jitter at 7.5 GHz (100 Hz to 100 MHz). It lists a PLL figure of merit of −236 dBc/Hz, normalised 1/f noise of −129 dBc/Hz, a 32-bit fractional-N divider and phase-detector frequency up to 400 MHz in integer mode and 300 MHz in fractional mode. [1]

The datasheet gives the PLL noise as the combination of a flat component, PLL_flat = PLL_FOM + 20·log(Fvco/Fpd) + 10·log(Fpd/1 Hz), and a flicker component, PLL_flicker = PLL_flicker_Norm + 20·log(Fvco/1 GHz) − 10·log(offset/10 kHz), summed in power. It also offers a programmable input multiplier to move integer-boundary spurs and an N-divider without a pre-divider to reduce spurs. [1]

Editorial calculation: with the datasheet's −236 dBc/Hz FOM and −129 dBc/Hz 1/f figure, a 12 GHz VCO at 100 MHz phase-detector frequency gives a flat floor of −236 + 20·log(120) + 80 ≈ −114.4 dBc/Hz and a 10 kHz flicker term of −129 + 20·log(12) ≈ −107.4 dBc/Hz, together about −106.6 dBc/Hz. Raising fPD to 200 MHz lowers the flat floor by about 3 dB. [1]

TI's lower-power LMX2572 shows the trade-off: it lists a −232 dBc/Hz figure of merit and −123.5 dBc/Hz normalised 1/f noise, against −236 and −129 dBc/Hz for the LMX2594, with −106 dBc/Hz phase noise at 100 kHz offset on a 6.4 GHz carrier and phase-detector frequency up to 250 MHz in integer mode and 200 MHz with a first- or second-order modulator. Its datasheet uses the same flat-plus-flicker model for PLL noise. [2] [1]

Renesas' 8V97003 also lists a −236 dBc/Hz figure of merit and runs its phase-frequency detector up to 500 MHz in integer mode and 250 MHz in fractional mode. At 6 GHz output, integrated jitter from 20 kHz to 100 MHz is 35 fs rms typical (50 fs maximum) with a 500 MHz integer-mode PFD, against 66 fs typical with a 245.76 MHz fractional-mode PFD. [3]

Editorial calculation: at a 6 GHz VCO and 100 MHz phase-detector frequency, the LMX2572's figures give a flat floor of −232 + 20·log(60) + 80 ≈ −116.4 dBc/Hz and a 10 kHz flicker term of −123.5 + 20·log(6) ≈ −107.9 dBc/Hz, together about −107.4 dBc/Hz; the LMX2594's figures give about −112.6 dBc/Hz at the same point, roughly 5 dB lower, because the LMX2594's figure of merit is 4 dB and its 1/f figure 5.5 dB lower. [2] [1]

Give the supplier the output frequency range and step size, number of outputs and output power, phase noise at your offsets or integrated jitter over your band, spur limits, reference frequency and level, frequency-switching or lock time, ramp or chirp needs, synchronisation or SYSREF needs, supply voltage and current budget, package and temperature range, and quantity.

02

Check reference input, switching time, power and package

The LMX2594 accepts a reference input of 5 to 1,400 MHz (5 to 200 MHz with the doubler on) at 0.2 to 2 Vpp AC-coupled, offers an input multiplier of 30–70 MHz in and 180–250 MHz out, and its calibration algorithm changes frequency in under 20 µs. It supports phase synchronisation across devices, SYSREF generation to JESD204B with 9 ps delay resolution, and frequency ramp and chirp generation for FMCW. [1]

It runs from a single 3.15–3.45 V supply with integrated LDOs, drawing 340 mA typical with one output at 14 GHz (5 mA powered down), over −40 to +85 °C ambient, in a 40-pin 6 × 6 mm VQFN with 30.5 °C/W junction-to-ambient resistance. Output power reaches 7 dBm at 15 GHz with an inductor pull-up, and crosstalk between outputs is −50 dBc. [1]

Switching time is stated differently by each maker. The LMX2572 lists VCO calibration of 130 µs with no assist, 50 µs with partial assist and 5 µs with full assist when switching between 3.2 and 6.4 GHz, and stays locked through a 125 °C temperature drift without recalibration. The 8V97003 lists 1 ms PLL lock time from chip-select to lock detect and 70 µs frequency-to-frequency lock when VCO calibration is bypassed. [2] [3]

Editorial calculation: 3.3 V × 0.34 A ≈ 1.1 W; at 30.5 °C/W that is a junction rise of about 34 °C, or about 119 °C at 85 °C ambient — close to the 125 °C junction limit, so board thermal design matters. [1]

Editorial calculation: the 8V97003 at 3.3 V × 0.516 A ≈ 1.70 W and 22.3 °C/W in still air rises about 38 °C, to about 133 °C at its 95 °C maximum ambient — above the 125 °C recommended junction temperature; at 2 m/s airflow (17.3 °C/W) the rise is about 29 °C, or about 124 °C. The LMX2572 at 3.3 V × 0.075 A ≈ 0.25 W stays far cooler. [3] [2]

03

Compare range, noise, power and package across parts

Renesas' 8V97003 is an mmWave wideband synthesizer with an integrated VCO that tunes an octave from 5.5 to 11 GHz; an output divider and an output doubler give 171.875 MHz to 18 GHz. It has a 32-bit fractional divider, accepts a reference from 10 MHz to 1.6 GHz (LVPECL, LVDS) or 10 to 250 MHz (LVCMOS) at 0.4 V to VDD peak-to-peak, and keeps output-to-output phase skew drift under 10° across conditions for beamforming. [3]

It runs from a single 3.135–3.465 V supply drawing 516 mA typical with one output active (590 mA maximum) and 566 mA with both, over −40 to +95 °C ambient with board temperature up to 105 °C and junction temperature up to 125 °C, in a 7 × 7 mm 48-VFQFPN. Output power reaches +12 dBm at 8 GHz and +4 dBm at 18 GHz with inductive loading, or +9.5 dBm and −2.5 dBm with 50-ohm resistive loading, and is below −80 dBm when muted. Storage temperature is −65 to 150 °C. [3]

The LMX2572 targets lower power: 12.5 MHz to 6.4 GHz from a 3.2–6.4 GHz VCO without an internal doubler, 75 mA typical at 3.3 V (2.5 mA powered down), a 5 to 250 MHz reference input, FSK modulation for digital radios and wireless microphones, phase synchronisation and JESD204B SYSREF, and a 6 × 6 mm 40-pin VQFN with 25.5 °C/W junction-to-ambient resistance over −40 to 85 °C. [2]

At the low-power end, a PLL need not be a separate catalogue chip. Mandal, Maj and Deptuch describe an integer-N synthesizer designed in 65 nm CMOS for on-chip clock generation: a PLL with a dual-tuned LC VCO, programmable feedback divider and two output dividers that generates two independent low-jitter clocks between 30 MHz and 3 GHz, locked to a 10–50 MHz reference, for a total of 4.0 mW from 1.2 V and 0.8 V supplies. [4] Editorial calculation: the LMX2572 at 75 mA and 3.3 V uses about 248 mW, roughly 60 times as much, but covers 12.5 MHz to 6.4 GHz with fractional-N steps; an embedded integer-N block suits fixed clock plans inside an ASIC, while a catalogue synthesizer is what a buyer orders for a radio or test system. [4] [2]

04

Find suppliers

The companies in the manufacturer list below show this product on their own websites. Confirm the legal seller, factory and scope for your order.

Ask any supplier for phase-noise plots at your output frequency and phase-detector frequency, spur data and calibration or lock time; the 8V97003 datasheet, for example, gives PFD-related spurs of −83.2 dB typical in integer mode and −74.1 dB in fractional mode at 245.76 MHz PFD. [1] [3]

05

Trace what each block controls

This is a functional reference built from the sources cited; it is not one maker's specification.

06

Fill the specification fields with values for your system

A PLL synthesizer quotation needs values for your system. The table explains each field, gives published values where a reviewed source states them, and says what to obtain from the supplier.

07

Send the frequency, noise and system data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Output: [range; step; outputs; power]
Noise: [dBc/Hz at offsets; jitter band]
Spurs: [limits]
Reference: [MHz; level]
Switching: [µs]
Features: [sync; SYSREF; ramp]
Supply/package: [V; mA; package]
Quantity: [units]

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