A capacitor in a sample-and-hold circuit that stores and maintains the sampled analog voltage signal for a defined period.
| Parameter | Typical range | Notes & selection driver |
|---|---|---|
| Tolerance | ±1% to ±5% | |
| Capacitance | 100pF to 10nF (typical range) | |
| Voltage Rating | 50V to 200V | |
| Leakage Current | <1nA | |
| Dielectric Absorption | <0.01% to 0.1% | |
| Operating Temperature | -55°C to +125°C | |
| Temperature Coefficient | ±50ppm/°C to ±100ppm/°C |
Ranges are indicative industry figures for RFQ preparation, not a supplier commitment. Confirm every value and standard with the legal manufacturer before ordering.
This component is used in the following industrial products
An electronic circuit that samples an analog signal at a specific instant and holds that value constant for subsequent processing.
An electronic circuit that captures and holds an analog voltage signal at a specific instant in time for subsequent processing.
A practical evidence checklist for RFQ preparation and supplier evaluation.
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Manufacturer profiles associated with Hold Capacitor.
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Dielectric absorption causes a capacitor to slowly release or 'remember' a previous charge state, leading to voltage errors during the hold phase. Low dielectric absorption materials (e.g., polypropylene) are essential for high-accuracy S/H circuits to minimize this memory effect and ensure signal fidelity.
A larger capacitance reduces droop rate (voltage decay during hold) but increases acquisition time (time to charge during sample) and requires more drive current. A smaller capacitance allows faster sampling but is more susceptible to droop and noise. The value is optimized based on required sampling speed, hold duration, and accuracy.
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