Sample-and-Hold Circuit: Specifications and Applications

Product Specifications

Technical details and manufacturing context for Sample-and-Hold (S/H) Circuit

Definition

A sample-and-hold (S/H) circuit is a component used in analog-to-digital conversion (ADC) systems. It captures the instantaneous voltage of a continuous analog signal at a precise moment and maintains that voltage stable during the conversion process, preventing errors caused by signal changes. The circuit operates in two phases: during the sample phase, a switch closes, allowing the input voltage to charge a hold capacitor; during the hold phase, the switch opens, isolating the capacitor and preserving the sampled voltage. This ensures that the ADC receives a constant input, improving accuracy. The S/H circuit is critical in data acquisition systems, instrumentation, and communication equipment. It is typically implemented using CMOS or bipolar semiconductor technology, with a polymer capacitor for charge storage and a ceramic substrate for mounting. Key parameters include supply voltage (5 V DC ±10%), supply current (2–10 mA), input and output voltage ranges (0–5 V), acquisition time (1–10 µs), aperture delay (10–50 ns), aperture jitter (1–5 ps), droop rate (0.1–1 mV/ms), settling time (2–20 µs), input offset voltage (±0.5 to ±5 mV), and gain error (±0.01% to ±0.1%). Operating temperature range is -40 to 85 °C, storage range -55 to 125 °C, and typical package is SOIC-8. These values are reference ranges and must be verified for the specific model and application. Standards such as IEC 60721-3-1 and JEDEC MS-012 are referenced for environmental and packaging considerations, but do not imply certification. Always consult the manufacturer for exact specifications and compliance.

Working Principle

The S/H circuit operates in two phases. In the sample phase, the control signal closes the switch, connecting the input to the hold capacitor. The capacitor charges to the input voltage, following the analog signal. In the hold phase, the switch opens, disconnecting the input. The capacitor retains its charge, maintaining the voltage at the last sampled value. This held voltage is then presented to the ADC for conversion. The switch is typically a CMOS transistor, and the capacitor is a high-quality polymer type to minimize leakage. The aperture delay is the time between the hold command and the actual opening of the switch, and aperture jitter is the uncertainty in that delay. During hold, the voltage may droop due to capacitor leakage, characterized by the droop rate. The acquisition time is the time needed for the capacitor to charge to the input voltage within a specified accuracy. The settling time is the time for the output to stabilize after acquisition. These parameters determine the circuit's performance and suitability for specific sampling rates and accuracy requirements.

Common Materials

Semiconductor (CMOS/Bipolar), Polymer capacitor, Ceramic substrate

Technical Parameters

Parameter	Typical range	Notes & selection driver
Supply Voltage	5 ±10% V DC	Operating range for analog and digital sections
Supply Current	2–10 mA	Depends on output load and sampling rate
Input Voltage Range	0–5 V	Within supply rails; beyond may cause clipping
Output Voltage Range	0–5 V	Holds last sampled value
Acquisition Time	1–10 µs	Time to settle to 0.01% of final value
Aperture Delay	10–50 ns	Delay from hold command to actual sampling
Aperture Jitter	1–5 ps	Uncertainty in aperture delay
Droop Rate	0.1–1 mV/ms	Voltage decay in hold mode
Settling Time	2–20 µs	To 0.01% after acquisition
Input Offset Voltage	±0.5–±5 mV	Affects accuracy
Gain Error	±0.01–±0.1 %	Full-scale error
Operating Temperature Range	-40–85 °C	Extended range availableIEC 60721-3-1
Storage Temperature Range	-55–125 °C	Non-operatingIEC 60721-3-1
Package Type	SOIC-8	Other packages availableJEDEC MS-012

Ranges are indicative industry figures for RFQ preparation, not a supplier commitment. Confirm every value and standard with the legal manufacturer before ordering.

Components / BOM

Analog Switch Part
Controls connection between input signal and hold capacitor

Material: CMOS/Bipolar semiconductor
Hold Capacitor Part
Stores sampled analog voltage during hold phase

Material: Polymer/ceramic dielectric
Buffer Amplifier
Isolates hold capacitor from loading effects and provides low-impedance output

Material: Semiconductor (op-amp circuitry)

Applied To / Applications

This component is essential for the following industrial systems and equipment:

Analog Input Section

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Frequently Asked Questions

What is the purpose of a sample-and-hold circuit?

It captures an analog voltage at a specific instant and holds it constant during analog-to-digital conversion, preventing errors due to signal changes.

What are the key parameters to consider when selecting a sample-and-hold circuit?

Important parameters include acquisition time, aperture delay, aperture jitter, droop rate, settling time, input offset voltage, and gain error. These affect accuracy and speed.

How does the hold capacitor affect performance?

The capacitor's quality determines droop rate and acquisition time. A low-leakage capacitor reduces droop, while a larger capacitance may increase acquisition time.

What standards apply to sample-and-hold circuits?

Environmental and packaging standards such as IEC 60721-3-1 and JEDEC MS-012 may be referenced, but compliance must be verified with the manufacturer.

Data Basis

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pressure:	Not applicable (electronic circuit, no fluid/gas pressure)
other spec:	Sampling rate: up to 100 MS/s (mega-samples per second) for high-speed versions, Hold time: typically 1 µs to 100 ms depending on capacitor and leakage
temperature:	-40°C to +125°C (operational range for typical IC implementations)

Sample-and-Hold (S/H) Circuit

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