Sample and Hold Circuit

Product Specifications

Technical details and manufacturing context for Sample and Hold Circuit

Definition

A sample and hold circuit is a component used in analog-to-digital conversion and other data acquisition systems. It captures the instantaneous voltage of an analog input signal at a precise moment and maintains that voltage level stable during the conversion process, ensuring that the analog-to-digital converter (ADC) receives a constant input while digitizing. The circuit operates in two phases: during the sample phase, a switch (typically a MOSFET) closes, connecting the input signal to a holding capacitor, which charges or discharges to the input voltage. In the hold phase, the switch opens, isolating the capacitor, which retains the sampled voltage due to its charge storage. This stable voltage is then presented to the ADC's quantizer. Key parameters include acquisition time (1-10 µs), aperture delay (10-50 ns), aperture jitter (1-10 ps RMS), hold capacitance (10-1000 pF), droop rate (0.1-10 mV/ms), input offset voltage (0.1-5 mV), gain error (0.01-0.1% of full scale), power supply voltage (±5 to ±15 V dual or 5-30 V single), power consumption (10-500 mW), operating temperature range (-40 to +85 °C), input and output voltage ranges (0 to Vcc-1.5 V for single supply), input impedance (10^12 Ω), output impedance (0.1-10 Ω), settling time (1-20 µs), sample/hold switch leakage (1-100 pA), charge injection (0.1-10 pC), and package types (SOIC-8, DIP-8, SOT-23-5). The circuit is subject to standards such as IEC 60748-4, JESD22-A104, and MIL-STD-883. These standards serve as verification references; actual compliance must be confirmed with the manufacturer. For any application, verify model-specific values and standards with the legal manufacturer or supplier.

Working Principle

The circuit operates in two phases. In the sample phase, a switch (typically a MOSFET) closes, connecting the input signal to a holding capacitor, allowing it to charge or discharge to the input voltage. In the hold phase, the switch opens, isolating the capacitor, which then maintains the sampled voltage due to its charge storage. This stable voltage provides a constant input for the ADC's quantizer. The acquisition time (1-10 µs) is the time for the capacitor to charge to within 0.1% of the input voltage. Aperture delay (10-50 ns) is the delay from hold command to switch opening, and aperture jitter (1-10 ps RMS) is its variation. The hold capacitance (10-1000 pF) determines droop rate and acquisition time trade-off. Droop rate (0.1-10 mV/ms) is the voltage decay on the capacitor due to leakage. Settling time (1-20 µs) is the time to settle to 0.01% of final value after hold command. Charge injection (0.1-10 pC) occurs when the switch opens, causing pedestal error.

Common Materials

Semiconductor (Silicon), Capacitor (e.g., Poly-Si, Metal)

Technical Parameters

Parameter	Typical range	Notes & selection driver
Acquisition Time	1-10 µs	1-10 — Time for the capacitor to charge to within 0.1% of the input voltage. Time for the capacitor to charge to within 0.1% of the input voltage.
Aperture Delay	10-50 ns	10-50 — Delay from hold command to switch opening. Delay from hold command to switch opening.
Aperture Jitter	1-10 ps RMS	1-10 — Variation in aperture delay, affects SNR at high frequencies. Variation in aperture delay, affects SNR at high frequencies.
Hold Capacitance	10-1000 pF	10-1000 — Determines droop rate and acquisition time trade-off. Determines droop rate and acquisition time trade-off.
Droop Rate	0.1-10 mV/ms	0.1-10 — Voltage decay rate on the hold capacitor due to leakage. Voltage decay rate on the hold capacitor due to leakage.
Input Offset Voltage	0.1-5 mV	0.1-5 — DC offset between input and held voltage. DC offset between input and held voltage.
Gain Error	0.01-0.1 % of full scale	0.01-0.1 — Deviation from ideal gain of 1. Deviation from ideal gain of 1.
Power Supply Voltage	±5–±15 V	±5 to ±15 — Dual supply typical; single supply options available. Dual supply typical; single supply options available.
Power Consumption	10-500 mW	10-500 — Depends on speed and architecture. Depends on speed and architecture.
Operating Temperature Range	-40–+85 °C	-40 to +85 — Industrial grade; extended ranges available. -40 to +85 — Industrial grade; extended ranges available. Outside this range: Performance degrades; offset and gain errors increase, droop rate worsens.
Input Voltage Range	0 to Vcc-1.5 V	0 to Vcc-1.5 — For single supply; for dual supply, typically ±Vcc. For single supply; for dual supply, typically ±Vcc.
Output Voltage Range	0 to Vcc-1.5 V	0 to Vcc-1.5 — Must match ADC input range. Must match ADC input range.
Input Impedance	10^12 Ω	10^12 — High impedance FET input. High impedance FET input.
Output Impedance	0.1-10 Ω	0.1-10 — Low output impedance for driving ADC. Low output impedance for driving ADC.
Settling Time	1-20 µs	1-20 — Time to settle to 0.01% of final value after hold command. Time to settle to 0.01% of final value after hold command.
Sample/Hold Switch Leakage	1-100 pA	1-100 — Leakage current when switch is open. Leakage current when switch is open.
Charge Injection	0.1-10 pC	0.1-10 — Charge transferred to capacitor when switch opens, causes pedestal error. Charge transferred to capacitor when switch opens, causes pedestal error.
Package Type	SOIC-8, DIP-8, SOT-23-5	SOIC-8, DIP-8, SOT-23-5 — Depends on supplier and part. Depends on supplier and part.
Supply Voltage	±5–±15 V (dual) or 5-30 V (single)	±5 to ±15 V (dual) or 5-30 V (single) — Outside this window: Out of range may cause clipping, increased distortion, or device damage.
Input Signal Frequency	DC to 10 MHz (for 1 µs acquisition)	Outside this window: Above bandwidth, sampling accuracy degrades due to insufficient settling.
Input Signal Amplitude	0 to Vcc-1.5 V (single supply)	Outside this window: Exceeding range causes nonlinearity and potential damage.
Hold Time	1 µs to 10 ms	Outside this window: Longer hold times increase droop error beyond acceptable limits.

Ranges are indicative industry figures for RFQ preparation, not a supplier commitment. Confirm every value and standard with the legal manufacturer before ordering.

Components / BOM

Sampling Switch Part
Connects/disconnects the input signal to/from the holding capacitor based on control signal

Material: Semiconductor (MOSFET)
Holding Capacitor Part
Stores the sampled analog voltage charge during the hold phase

Material: Poly-Silicon or Metal-Insulator-Metal (MIM)
Buffer Amplifier
Provides high input impedance during sampling and low output impedance during holding to drive the ADC

Material: Semiconductor (Op-amp circuit)

Applied To / Applications

This component is essential for the following industrial systems and equipment:

Analog-to-Digital Converter (ADC)

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ADC Converter

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A/D Converter

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ADC (Analog-to-Digital Converter)

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A/D Converter (if applicable)

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ADC/DAC Converter

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Signal Converter (ADC/DAC)

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Sampler/Decision Circuit

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Manufacturers of Sample and Hold Circuit

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Frequently Asked Questions

What is the primary function of a sample and hold circuit?

It captures the instantaneous voltage of an analog signal at a specific moment and holds it constant during the conversion process, ensuring the ADC sees a stable input.

What are the two operating phases of a sample and hold circuit?

Sample phase: switch closes, capacitor charges to input voltage. Hold phase: switch opens, capacitor retains voltage, providing stable input to ADC.

What is aperture delay and why is it important?

Aperture delay is the time from the hold command to the switch opening (10-50 ns). It affects the accuracy of the sampled instant, especially at high frequencies.

How does droop rate affect performance?

Droop rate (0.1-10 mV/ms) is the voltage decay on the hold capacitor due to leakage. It limits the maximum hold time before the voltage drifts beyond acceptable error.

Data Basis

Editorial classification, named public sources where available, and source-reviewed manufacturer records.

Preliminary Technical Classification

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