Identify the physical IF stage before selecting its filter paths
An intermediate-frequency filter bank provides selectable filtering paths within a receiver. In a swept spectrum-analyzer chain, the selected analog resolution filter operates on the converted IF signal. Specify the bank as an assembly matched to that signal path, with a response and control state for every ordered bandwidth.
Physical IF filter-bank assemblies and boards for spectrum-analyzer receiver chains, including selectable analog resolution-bandwidth paths and their switching/interfaces. Complete analyzers, RF input preselector banks, single RF cavity filters and software-only FFT/DSP filter banks are separate scopes. An analog prefilter ahead of a digitizer requires its own defined receiver role.
01
Tektronix’s instrumentation diagrams distinguish the swept analyzer’s resolution-filter path from the broader IF filter ahead of a vector analyzer’s ADC. Identify which function the ordered assembly must perform. [1]
Obtain the host analyzer or receiver model, hardware revision and IF block diagram. For an OEM replacement, confirm the assembly part/revision and any required calibration or firmware compatibility.
In a swept receiver the mixer/local-oscillator plan translates the input signal into the IF path. Define the bank’s IF centre frequency and selectable responses separately from the analyzer’s RF tuning range.
Keysight’s 89600 help distinguishes analog IF resolution filtering from the digital IF/DSP implementation of its VSA software. A displayed RBW setting can therefore require a digital processing configuration rather than another physical filter element. [2]
02
Order a state schedule that connects each control command to an identifiable IF path and its measured response.
For each path, specify centre frequency, bandwidth definition, passband loss/ripple, transition regions and stopband intervals. Use explicit attenuation points or a response mask rather than an unqualified bandwidth number.
Measure at the delivered assembly reference planes, with the specified source/load impedances and operating level. Include switch and matching-network losses in the assembly requirement; record any fixture removal or de-embedding used in the report.
Define control voltage/interface, state encoding, default behaviour and any bypass path. Agree switching and settling criteria, including the output condition during transitions and the point at which a result may be accepted.
03
Rohde & Schwarz’s 2013 note describes analog prefiltering ahead of an ADC even where resolution filtering is digital. It also relates narrow resolution-filter settling to sweep timing. Keep both physical-path loading and timing in the integration review. [3]
Specify the permitted signal level at the bank, including blockers and total composite input. Confirm the downstream amplifier/ADC operating limits, overload margin and the bank’s own power-handling conditions.
After installation, verify the state selection and response before accepting host-level amplitude or bandwidth performance. Apply the host manufacturer’s calibration and verification procedure for the changed assembly.
Record the hardware revision, control settings, temperature and measurement setup used for each result. Distinguish assembly insertion loss and rejection from the complete analyzer’s noise floor, sensitivity and dynamic range.
04
This functional reference identifies the assembly topics to document. Its circuit implementation and filter technology must come from the actual design.
| Function | Define for the assembly | Evidence |
|---|---|---|
| Bandpass filter elements / paths | IF centre, ordered bandwidth states and transfer-function requirements. | State-specific response masks and measured traces. |
| Switching network | Selected path, control logic and transition/default behaviour. | State table, electrical interface and switching/settling tests. |
| Impedance matching and interconnect | Source/load terminations and signal route through the bank. | Interface drawing, reference planes and assembly response. |
05
Use a path identifier with every electrical response. Confirm which limits apply over temperature, signal level and frequency rather than copying the host instrument’s headline specifications.
| Field | Define for the selected path | Acceptance evidence |
|---|---|---|
| Centre frequency (MHz) | Nominal IF and allowed shift under stated conditions. | Measured centre/response for the assembly state. |
| Bandwidth (Hz / MHz) | Width and its attenuation or equivalent-noise definition. | Declared metric, tolerance and response trace. |
| Insertion loss (dB) | Reference level, frequency and included switches/interfaces. | Port-plane transmission measurement at stated power. |
| Passband ripple (dB) | Passband interval and peak-to-peak definition. | Response trace and accepted mask. |
| Stopband rejection (dB) | Frequency intervals/offsets and reference level. | Measured rejection with adequate test-system range. |
| Input/output impedance (Ω) | Required terminations and permitted mismatch. | Return-loss/impedance data at defined planes. |
| Operating temperature (°C) | Powered assembly conditions for guaranteed response. | Performance evidence over the specified conditions. |
| Storage temperature (°C) | Non-operating exposure and recovery requirements. | Applicable environmental evidence. |
| Relative humidity (% RH) | Condensation status, exposure and enclosure conditions. | Assembly/material compatibility and relevant testing. |
| Power handling (W / dBm) | CW/pulse/composite level, duration and temperature. | Rated input limits and any power-dependent response. |
| Connector / board interface | Connector sex, pinout, footprint and grounding. | Interface drawing matched to the host. |
| Dimensions (mm) | Mounting, shield/enclosure and connector clearances. | Controlled mechanical drawing. |
| Weight (g) | Delivered assembly and mounting scope. | Model/revision-specific mass. |
| Selection control and calibration | Logic levels, state table, settling and host revision. | Control tests and installed verification/calibration record. |
06
Paste it into your enquiry below or into an email to a maker, then replace every bracket.
Host: [analyzer/receiver model; hardware/firmware revision; assembly identity] Function: [analog RBW bank or defined ADC prefilter; IF centre; signal levels] States: [control code; bandwidth metric; response mask; bypass/default] Interfaces: [impedance; connectors/footprint; control supply; grounding] Conditions: [temperature; humidity; CW/pulse/composite power; mounting] Acceptance: [per-state response; switching/settling; installed calibration]
Provide the receiver block diagram, assembly revision and per-state filter requirements. Ask the supplier to confirm its circuit scope, control interface, port-plane response and the installed verification needed for the proposed host.
Explore company information and manufacturing capabilities, then discuss the scope of your project with a relevant supplier.
Confirm the architecture: Keysight describes digital IF/DSP resolution filtering in its VSA implementation. [2]
Specify the stage and function from the host receiver diagram. [1]
Use the path and bandwidth metric with its response limits; Keysight distinguishes equivalent-noise, −3 dB and −6 dB metrics in its software. [2]
Verify the selected response, settling and host calibration under the applicable equipment procedure. [3]
Sources checked 2026-10-19. The cited instrument-maker documents establish analog, digital and prefilter roles. They provide architecture and measurement context; obtain an assembly-specific drawing, rating and acceptance report for the bank being ordered.
Ask for use case, specification boundaries, supplier type, and RFQ preparation information for this product.
Compare manufacturer profiles with relevant product and process capability.