INDUSTRY COMPONENT

Plated Through Holes

Plated Through Holes (PTH) are conductive pathways drilled through PCB layers and electroplated with copper to create electrical connections between different layers in high-density interconnect substrates.

Component Specifications

Definition
Plated Through Holes (PTH) are fundamental interconnect structures in multilayer printed circuit boards (PCBs), particularly critical in High-Density Interconnect (HDI) substrates. These are precisely drilled holes that penetrate through multiple PCB layers, then undergo a comprehensive electroplating process where copper is deposited along the hole walls to establish reliable electrical continuity between different conductive layers. The plating process typically involves electroless copper deposition followed by electrolytic copper plating to achieve the required thickness and conductivity. PTHs enable three-dimensional routing of electrical signals in complex electronic assemblies, supporting miniaturization and increased functionality in modern electronic devices.
Working Principle
PTHs function by creating conductive pathways through insulating PCB substrate materials. After mechanical or laser drilling creates holes through the PCB stack-up, the hole walls undergo surface preparation and activation. Electroless copper deposition establishes a thin conductive seed layer, followed by electrolytic copper plating that builds up the required copper thickness. This creates continuous conductive barrels that connect copper traces on different layers, allowing electrical signals and power to pass vertically through the PCB structure while maintaining mechanical integrity.
Materials
Primary: Electrolytic copper (99.9% purity) with typical thickness 25-35 μm. Substrate: FR-4, polyimide, or other PCB dielectric materials. Plating chemistry: Copper sulfate-based electrolytes with proprietary additives for throwing power and uniformity. Barrier/seed layer: Electroless copper (0.5-1.5 μm). Surface finish options: HASL, ENIG, Immersion Silver, OSP, or ENEPIG.
Technical Parameters
ParameterTypical rangeNotes & selection driver
Aspect RatioUp to 10:1
Plating Voids<5%
Thermal CyclingPasses 1000 cycles (-40°C to +125°C)
Copper Thickness25-35 μm
Hole Diameter Range0.15-0.8 mm
Insulation Resistance>10^9 Ω
Registration Accuracy±0.05 mm
Current Carrying Capacity1-3A per hole (depending on diameter)

Ranges are indicative industry figures for RFQ preparation, not a supplier commitment. Confirm every value and standard with the legal manufacturer before ordering.

Standards
IPC-6012, IPC-A-600, IPC-4552, ISO 9001, IEC 61189

Parent Products

This component is used in the following industrial products

Engineering Analysis

Risks & Mitigation
  • Plating voids reducing conductivity
  • Thermal stress cracking
  • Poor hole wall adhesion
  • Drilling smear causing plating defects
  • Barrel cracking during thermal cycling
  • Insufficient copper thickness
FMEA Triads
Trigger: Inadequate hole cleaning before plating
Failure: Poor copper adhesion and plating voids
Mitigation: Implement optimized desmear and cleaning processes with process controls and regular chemical analysis
Trigger: Excessive thermal expansion mismatch
Failure: Barrel cracking during temperature cycling
Mitigation: Use matched CTE materials, optimize plating thickness, and implement gradual thermal profiles during assembly
Trigger: Insufficient plating solution agitation
Failure: Non-uniform copper deposition and thin spots
Mitigation: Implement proper solution circulation, optimize racking density, and use pulse plating techniques

Industrial Ecosystem

Compatible With

Typical Suppliers & Equivalents

Compliance & Inspection

Tolerance
Hole diameter: ±0.05 mm, Position: ±0.075 mm, Copper thickness: +0/-10% of nominal
Test Method
IPC-TM-650 test methods, cross-section analysis per IPC-6012, thermal stress testing per IPC-TM-650 2.6.8, electrical continuity testing

Procurement Evaluation Criteria

A practical evidence checklist for RFQ preparation and supplier evaluation.

Technical documentation
Request current drawings, revision history, and a signed specification sheet.
Manufacturing capability
Verify equipment lists, process limits, capacity, and representative production evidence.
Inspection readiness
Confirm test methods, calibrated equipment, sampling plans, and traceable reports.
Supplier transparency
Check the legal entity, factory address, ownership, certifications, and direct contacts.

CNFX does not score or rank suppliers. Buyers must verify all claims and documents with the legal manufacturer before ordering.

Manufacturers of Plated Through Holes

Manufacturer profiles associated with Plated Through Holes.

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Frequently Asked Questions

What is the difference between PTH and blind/buried vias?

PTHs penetrate through the entire PCB thickness, connecting all layers, while blind vias connect an outer layer to one or more inner layers without going through the entire board, and buried vias connect only inner layers without reaching either surface.

What causes plating voids in PTHs?

Plating voids typically result from inadequate hole cleaning, poor activation, air bubbles trapped during plating, or insufficient throwing power of the plating solution, leading to incomplete copper deposition along the hole walls.

How are PTHs tested for quality?

PTH quality is verified through cross-section microscopy, automated optical inspection (AOI), electrical continuity testing, thermal stress testing, and microsection analysis to check plating thickness, voids, and adhesion.

Data Basis

Editorial classification, named public sources where available, and source-reviewed manufacturer records. See the editorial policy.

Preliminary Technical Classification
This page supports structured research, RFQ preparation, and supplier evaluation. It does not replace buyer-led supplier qualification, standards review, or technical approval.

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