Multilayer PCB (rigid multilayer printed circuit board)

01

Choose the laminate for the assembly temperatures

Isola describes its 370HR laminate and prepreg as a 180 °C Tg multifunctional epoxy, lead-free compatible and qualified to IPC-4101 /98, /99, /101 and /126. Its typical values are Tg 180 °C by DSC, decomposition temperature (Td, 5% weight loss) 340 °C, time to delamination of 60 minutes at 260 °C (T260) and 30 minutes at 288 °C (T288), Z-axis CTE of 45 ppm/°C below Tg and 230 ppm/°C above, with 2.8% total expansion from 50 to 260 °C, X/Y CTE of 13/14 ppm/°C, moisture absorption 0.15% and UL 94 V-0 with a relative thermal index of 130 °C. [1]

Isola lists Dk falling from 4.24 at 100 MHz to 3.92 at 5 and 10 GHz and Df rising from 0.0150 to 0.0250 over the same range, and peel strength of 1.14 N/mm for standard-profile copper after thermal stress. [1] Editorial note: compare laminates on the same test methods; Tg alone does not show how a board survives repeated reflow, which Td, T260/T288 and Z-axis expansion describe.

Editorial calculation: 2.8% Z-axis expansion from 50 to 260 °C means a 1.6 mm board grows about 45 µm through its thickness during a reflow excursion, which the copper in each plated through-hole must follow; ask the fabricator for plated-hole copper thickness and thermal-stress or interconnect-stress test results on your stack-up. [1]

Give the fabricator the Gerber and drill files, layer count and stack-up with dielectric thicknesses, laminate (or required Tg, Td, T260/T288 and Dk/Df), copper weights, minimum trace, space and drill size, impedance targets and tolerance, surface finish, solder mask colour, board thickness and tolerance, IPC class, quantity and test requirements (electrical test, impedance coupons, microsections).

02

Compare a second laminate maker's FR-4 grades

Shengyi Technology, a Chinese copper-clad laminate maker, publishes typical values for its S1000-2 lead-free compatible FR-4.0 laminate, referenced to specification sheet IPC-4101/126 and measured on 1.6 mm specimens. Its table gives Tg 180 °C by DSC and 185 °C by DMA, Td (5% weight loss) 345 °C, Z-axis CTE of 45 ppm/°C below Tg and 220 ppm/°C above with 2.8% expansion from 50 to 260 °C, T260 of 60 minutes, T288 of 20 minutes and T300 of 5 minutes, and 100 s at 288 °C solder dip with no delamination. [4] The same page lists Dk 4.8 and Df 0.013 at 1 MHz, peel strength of 1.38 N/mm after thermal stress at 288 °C for 10 s and 1.07 N/mm at 125 °C, water absorption 0.10%, CTI PLC 3 and UL 94 V-0; its Chinese-language feature list gives Tg 170 °C (DSC) while the table gives 180 °C, so confirm the Tg figure on the certified data sheet. [4]

Shengyi's lower-Tg S1000 grade lists Tg 155 °C, Td 335 °C, Z-axis CTE of 49 and 250 ppm/°C with 3.4% expansion from 50 to 260 °C, T260 above 60 minutes and T288 of 10 minutes, Dk 4.7 and Df 0.009 at 1 GHz and water absorption 0.09%. [5] Editorial calculation: on a 1.6 mm board, 2.8% expansion is about 45 µm and 3.4% about 54 µm, so the S1000 grade asks roughly 9 µm more stretch of each plated through-hole per reflow excursion; for high-layer-count boards with two or more reflow passes, the S1000-2 and 370HR class (T288 of 20 and 30 minutes) leaves more margin than a 155 °C Tg grade. [4] [5] [1]

03

Guard against CAF with spacing and laminate choice

Isola's paper on conductive anodic filament (CAF) failure describes it as copper electromigration that bridges two oppositely biased conductors, in four modes — hole to hole, line to line, hole to line and layer to layer — and states that "the most common failure mode is hole to hole". It states mean time to failure depends on bias voltage, relative humidity, hole-to-hole and line-to-line spacing, temperature and the resin system, and that failure begins with degradation of the resin–glass interface followed by irreversible electrochemical migration. [2]

Isola's test vehicle was a four-layer board with hole spacings from 0.006 to 0.035 inch, held at 85 °C/85% RH under bias with resistance read every 96 hours; a second series on materials with Tg above 170 °C used 24 mil hole-to-hole spacing and 13.5 V and 100 V bias. It reports that glass finish and resin system affect insulation resistance. [2] Isola describes 370HR as built with E-glass fabric for CAF resistance. [1]

Editorial calculation: 0.006 in is about 0.15 mm and 0.035 in about 0.89 mm, so the tested spacings span the tight pitches of dense designs; for boards that will see humidity and bias in service, ask the fabricator for CAF test data at your minimum hole-to-hole spacing and voltage. [2]

04

Compare what suppliers offer

Suppliers linked to this page list multilayer PCBs; each card links to the page reviewed.

Listings include high-layer-count and high-precision multilayer boards, impedance-controlled multilayers, and fabricators that also build HDI, flex, rigid-flex and metal-core boards; ask each for laminate options, stack-up capability, CAF and reliability test data.

05

Write a reflow-simulation test into the purchase order

IPC's test method 2.6.27B simulates convection reflow assembly on coupons built with the board's largest plated through-holes, smallest vias, planes and via structures. Specimens are first dried for at least six hours at 105 to 125 °C, then put through a minimum of six reflow cycles, cooling to 45 °C or below between cycles. The default profile targets a 260 ± 5 °C peak with a 230 °C maximum preheat and a maximum preheat rate of 2.0 °C per second; low-temperature (230 ± 5 °C) and 245 ± 5 °C profiles are also defined. [3]

Evaluation is by microsection against the applicable performance specification (for example IPC-6012 for rigid boards), or by resistance change on IPC-2221 D-coupons, logged at least once per second per net. IPC sets the maximum allowable resistance change at 5% unless otherwise specified, and asks that cycles to failure be documented. Its example drawing note requires D-coupons to pass 6 reflow simulations on the 230, 245 or 260 °C profile with acceptance at < 5% change in resistance. [3]

Editorial note: pick the profile that matches your own assembly peak, and add the drawing note to your fabrication drawing so every lot is tested against it; ask for the count of coupons tested per manufacturing panel and for the resistance-change report. [3]

06

Trace the board layers

This is a functional reference built from the sources cited; it is not one maker's specification.

07

Fill the specification fields with values for your board

A multilayer PCB quotation needs values for your board. The table explains each field, gives published values where a reviewed source states them, and says what to obtain from the supplier.

08

Send the stack-up, laminate and reliability needs together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Files: [Gerbers; drill; stack-up]
Laminate: [grade or Tg, Td, T260/T288, Dk/Df]
Geometry: [layers; thickness; copper; trace/space; drill]
Impedance: [targets; tolerance]
Finish: [surface finish; mask]
Reliability: [IPC class; CAF data; thermal stress]
Test: [electrical test; coupons; microsections]

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