Stereo audio DAC ICs · Dynamic range, SNR and THD+N grades, sample rates and word lengths, I²S and left-justified inputs, integrated PLL versus external system clock, ground-centred line outputs, digital filter latency, supplies and automotive qualification
An audio DAC (digital-to-analog converter) is an integrated circuit that converts digital audio samples, received over a serial interface such as I²S, into analog line-level signals for amplifiers, speakers or headphones; stereo audio DACs add digital filters, clock circuits, muting and output drivers. Ask three things first: what dynamic range, signal-to-noise ratio and distortion the product's audio chain needs, what sample rates, word lengths, data format and clocking the host provides, and what output level, load, supply and qualification the design requires.
Stand-alone stereo and multichannel audio DAC ICs for consumer, professional and automotive audio. Audio codecs combining ADC and DAC (see audio codec), precision industrial DACs (see DAC digital-to-analog converter), Class-D amplifiers, audio DSPs and finished DAC modules are outside this page except where compared.
01
Texas Instruments' data sheet for the PCM510xA family (SLAS859C) lists three pin-compatible stereo audio DACs in a 20-pin TSSOP (5.50 × 4.40 mm): PCM5102A with 112 dB dynamic range and SNR and −93 dB THD+N at −1 dBFS, PCM5101A with 106 dB and −92 dB, and PCM5100A with 100 dB and −90 dB, all at a 3.3 V supply. It describes a segment-DAC architecture with improved tolerance to clock jitter and up to 20 dB lower out-of-band noise than conventional switched-capacitor designs, measured from 100 kHz to 3 MHz, and AEC-Q100-qualified -Q1 versions for automotive infotainment. [1]
For comparison, Cirrus Logic's CS4344 family (CS4344, CS4345, CS4348) is a 10-pin TSSOP stereo DAC with a fourth-order multibit delta-sigma modulator, 24-bit conversion, sample rates detected automatically up to 192 kHz, 105 dB dynamic range and −90 dB THD+N. It runs from a single +3.3 V or +5 V supply and includes interpolation, on-chip analog filtering, digital de-emphasis and what Cirrus calls Popguard technology. It is offered in commercial (−10 to +85 °C) and automotive (−40 to +85 °C) grades. [2]
Editorial note: choose the grade from the noise and distortion the rest of the chain can actually use — amplifier, speakers and enclosure — and ask suppliers for the measurement conditions (bandwidth, weighting, load) behind each figure so grades from different makers can be compared.
Give the supplier the channel count, required dynamic range, SNR and THD+N with measurement conditions, sample rates and word lengths, data format (I²S, left-justified, TDM), whether a system (master) clock is available, output type and level, load impedance, supply voltages, package, temperature range and automotive qualification needs, and annual quantity.
02
The PCM510xA accepts 16-, 24- and 32-bit data in I²S or left-justified formats at sampling frequencies of 8–384 kHz, supports system-clock multiples from 64 to 3,072 × fS up to 50 MHz, and integrates a PLL that generates the system clock from the bit clock so a 3-wire I²S connection is enough, which the data sheet says reduces EMI. A charge-pump (DirectPath) line driver gives 2.1 VRMS ground-centred outputs into loads down to 1 kΩ per pin without DC-blocking capacitors; muting is soft-ramped with analog mute, and the device enters power-save when the clocks stop. It runs from a single 3.3 V analog supply with 1.8 V or 3.3 V failsafe digital inputs, and is configured with hardware pins. [1]
The I²S bus that these DACs accept is defined in NXP's I²S bus specification (UM11732, Rev. 3.0, 2022). It has three lines: a continuous serial clock (SCK), word select (WS) and serial data (SD), and the device generating SCK and WS is the controller. WS = 0 carries channel 1 (left) and WS = 1 channel 2 (right). Data are sent in two's complement, MSB first, and WS changes one clock period before the MSB is transmitted. [3]
Variants of one family can differ only in data format. Cirrus Logic's selection guide lists the CS4344 for 16- to 24-bit I²S, the CS4345 for 16- to 24-bit left-justified and the CS4348 for 16-bit right-justified data. The CS4344 needs a master clock (MCLK) at an integer ratio to LRCK, from 0.512 to 50 MHz, unlike the PCM510xA's internal PLL. Its full-scale output is 0.65 × VA peak-to-peak typical, so the output level depends on the supply voltage. [2]
The normal 8× oversampling digital filter has a latency of 20 sample periods (tS) and the low-latency filter 3.5 tS. [1]
Editorial calculation: at 48 kHz one sample period is about 20.8 µs, so the normal filter adds about 20 × 20.8 ≈ 417 µs and the low-latency filter about 73 µs; a 2.1 VRMS sine output is about 5.9 V peak-to-peak (2.1 × 2√2). [1]
03
The companies in the manufacturer list below show this product on their own websites. Confirm the legal seller, factory and scope for your order.
04
ROHM's specification page for the BD34352EKV lists a 32-bit stereo audio DAC with 126 dB typical SNR and dynamic range and −112 dB typical THD+N in PCM mode, PCM sampling from 32 to 768 kHz, DSD input at 2.8, 5.6, 11.2 and 22.4 MHz, stereo or mono mode, and two selectable digital FIR filters (sharp roll-off and slow roll-off). ROHM states a rejection-band attenuation of −150 dB or less for its digital filter. [4]
The same page lists three supply ranges — 4.5 to 5.5 V for AVCC, 1.4 to 1.6 V for DVDD and 3.0 to 3.6 V for DVDDIO — a 2-wire control interface with four selectable device addresses, an operating range of −25 to 85 °C, and an HTQFP64BV package of 12 × 12 mm at moisture sensitivity level 3. [4]
Editorial calculation: 126 dB is 14 dB above the PCM5102A's 112 dB and 21 dB above the CS4344's 105 dB dynamic range. The ROHM part needs three supply rails where the PCM510xA runs from a single 3.3 V analog supply, and its −25 °C lower limit is narrower than the −40 to +85 °C automotive grade of the CS4344. [4] [1] [2] Editorial note: request the measurement conditions behind each figure.
05
This is a functional reference built from the source cited; it is not one maker's design.
| Function | Role | Fix in the order |
|---|---|---|
| Serial audio interface | Receives samples. [1] | Formats, word lengths. |
| Digital interpolation filter | Oversamples, sets latency. [1] | Filter options. |
| DAC core | Converts to analog. [1] | Grade, architecture. |
| PLL / clock | Generates internal clocks. [1] | System clock needs. |
| Line driver (charge pump) | Drives output. [1] | Level, load. |
| Mute and power management | Avoids pops, saves power. [1] | Behaviour, supplies. |
06
An audio DAC quotation needs values for your design. The table explains each field, gives published values where a reviewed source states them, and says what to obtain from the supplier.
| Field | What it means and published values | Ask the supplier for |
|---|---|---|
| Dynamic range / SNR | 112, 106 or 100 dB by grade. [1] | Values and conditions. |
| THD+N at −1 dBFS | −93, −92 or −90 dB by grade. [1] | Values and conditions. |
| Sample rate | 8–384 kHz. [1] | Supported rates. |
| Data | 16/24/32-bit, I²S or left-justified. [1] | Formats, TDM. |
| Clocking | Internal PLL from bit clock. [1] | Master clock needs. |
| Output | 2.1 VRMS ground-centred, ≥1 kΩ load. [1] | Level, load, coupling. |
| Supply | 3.3 V analog; 1.8 or 3.3 V digital. [1] | Supply range. |
| Qualification | AEC-Q100 -Q1 versions. [1] | Grade and temperature. |
07
Paste it into your enquiry below or into an email to a maker, then replace every bracket.
Performance: [dynamic range; SNR; THD+N] Interface: [format; word length; sample rates] Clocking: [master clock; PLL] Output: [level; load; coupling] Supply: [analog; digital] Qualification: [temperature; automotive; package; quantity]
This company lists this product on its own website.
Its website lists the ES7148 two-channel audio DAC.
Product scope checked 2026-10-12
Explore company information and manufacturing capabilities, then discuss the scope of your project with a relevant supplier.
One family offers 112, 106 or 100 dB dynamic range with THD+N of −93, −92 or −90 dB at −1 dBFS. [1]
Not always; one family integrates a PLL that generates the system clock from the I²S bit clock, allowing a 3-wire connection. [1]
It removes the need for DC-blocking capacitors on the output; one device gives 2.1 VRMS into loads down to 1 kΩ. [1]
Three: continuous serial clock (SCK), word select (WS, 0 = left, 1 = right) and serial data (SD), with data in two's complement, MSB first. [3]
No. TI's PCM510xA generates its clock from the bit clock with a PLL, while Cirrus Logic's CS4344 needs an MCLK at an integer ratio to LRCK. [1] [2]
ROHM lists its BD34352EKV at 126 dB typical SNR and dynamic range and −112 dB typical THD+N, with PCM sampling from 32 to 768 kHz and DSD input up to 22.4 MHz. [4]
Sources checked 2026-10-12. Datasheets from Texas Instruments (PCM510xA) and Cirrus Logic (CS4344 family), and NXP's I²S bus specification (read from an Internet Archive copy), show what an audio DAC specification covers; values for your order must come from the supplier's datasheet.
Ask for use case, specification boundaries, supplier type, and RFQ preparation information for this product.
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