Automated test equipment (ATE) for semiconductors

01

Size the tester's digital, analogue and power resources

Chroma lists its 3380 VLSI test system with 50/100 MHz clock and 50/100 Mbps data rate, 1,024 I/O pins (maximum 1,280), up to 1,024 sites in parallel, 32/64/128M pattern memory and 16M capture memory per pin, up to 256 VI sources, a time and frequency measurement unit, AD/DA, SCAN (up to 2G per chain) and ALPG embedded-memory options, STDF data output and converters for test programs from other tester platforms. Chroma names MCU, ADC/DAC mixed-signal, logic, smart card, CMOS image sensor, class-D power and LED driver ICs as applications. [1]

Its 3650 SoC/analogue test system lists 50/100 MHz clock and 100/200 Mbps (multiplexed) data rate, up to 640 digital I/O pins, 32M vector and 32M pattern-instruction memory, a per-pin parametric measurement unit (PPMU) and frequency measurement, scan to 2G depth per chain, an ALPG option for memory test, up to 40 high-voltage I/O pins, 32 device power supply (DPS) channels, and analogue options up to 1,000 V stacked (HVVI) and 320 A pulsed (MPVI ganged), with 16-bit ADDA, arbitrary waveform generator and digitiser, and audio-band mixed-signal options. Chroma describes it as air-cooled with a small footprint and able to accept device interface boards and probe cards from other testers through a conversion kit; each 64-pin board uses 16 pin-electronics ICs, each with 4 timing-generator channels. [2]

Editorial note: count the resources per device — digital pins, supplies, analogue and high-voltage channels — then multiply by the planned number of sites; the tester must have dedicated resources for every site if parallel test is not to slow down.

A second maker's platform shows how power and interface resources are now specified. Advantest lists for its V93000 EXA Scale SoC tester a DC Scale XPS256 device power supply that "scales from mA to >> 1000A" through ganging, an XPS128+HV card covering −10 V to +24 V for power and analogue devices, and a PMUX02 card for higher multi-site counts; all card types fit all test heads, from the CX class to the LX class, with water cooling and a test processor per pin. Its DUT Scale Duo interface switches between two DUT board sizes and, Advantest states, increases usable DUT board and probe card space by 50 percent or more and allows component heights over three times taller. [4]

Memory testers are specified by interface speed: Advantest lists its T5801 DRAM test system at up to 36 Gbps PAM3 and 18 Gbps NRZ for GDDR7, LPDDR6 and DDR6 devices and MRDIMM and CAMM modules. Editorial calculation: 36 Gbps PAM3 is twice the 18 Gbps NRZ figure, and both are 180 to 360 times the 100 Mbps data rate listed for Chroma's 3380 VLSI tester. [5] [1]

Give the supplier the device list (type, pin count, package or wafer), the test plan (functional, scan, memory, DC parametric, analogue, mixed-signal, RF, power), per-device resource needs (digital pins and data rate, DPS channels and current, analogue and high-voltage channels), test time targets, number of sites, handler or prober, temperature, data format (such as STDF) and any existing test programs to convert.

02

Plan parallel test, interface hardware and cost of test

The International Technology Roadmap for Semiconductors (2009 test chapter) breaks the cost of a test cell into a base cost (mechanical infrastructure, back-plane, operating software and central instruments), an interface cost (interface electronics, sockets and probe cards, including spares), power-supply cost, test-channel instrument cost and other costs such as floor space, and uses units per hour per cost as a figure of merit. It states that multi-site test raises throughput and spreads the base cost over more dies, that it needs dedicated rather than shared ATE resources, and that interface cost becomes very challenging at high bandwidth (2 Gbit/s) or high site counts (128 sites). [3]

It defines multi-site efficiency as M = 1 − (T_N − T_1)/((N − 1)·T_1), where T_1 is the test time for one device and T_N for N devices in parallel. Its example: a device with a 10 s single-site test time tested at 32 sites in 16 s has an efficiency of 98.06%. It adds that 98% is adequate for two and four sites but that 32 sites need much higher efficiency, because at 98% the 10 s test grows to 10.8 s at four sites but to 16.4 s at 32 sites. [3]

Editorial calculation: ignoring handler index time, one site at 10 s gives 3,600/10 = 360 devices per hour, while 32 sites in 16 s give 32 × 3,600/16 = 7,200 devices per hour — 20 times the throughput rather than 32. Ask the supplier for the handler or prober index time and add it to each test cycle before comparing quotations. [3]

Chroma also lists automatic test systems for power electronics and IC pick-and-place handlers within its semiconductor and power-electronics test ranges. [1]

03

Semiconductor testers versus power-supply test systems

Chroma ATE Inc. lists VLSI and SoC/analogue semiconductor test systems alongside IC pick-and-place handlers; Dongguan Chuangrui New Energy Co., Ltd. lists power-supply, inverter and EVSE test systems rather than chip testers, so it fits only the power-electronics part of this page.

04

What sits in a test cell, from mainframe to handler

05

Tester resources to state per device and per site

Channel, memory and supply figures below are from Chroma's 3380 and 3650 pages and the throughput example from the ITRS chapter; per-instrument accuracy was not published in these sources.

06

Send the device, test plan and production data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Devices: [type; pins; package or wafer]
Tests: [digital; scan; memory; DC; analogue; mixed-signal; power]
Resources per device: [pins; DPS; analogue; HV]
Production: [sites; test time; handler or prober; temperature]
Software: [language; existing programs; STDF]
Supply: [installation; training; service; quantity]

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