Clock and data recovery (CDR) circuit

01

Match the data rates and the channel reach

TI's DS250DF410 datasheet describes a four-channel multi-rate retimer with integrated signal conditioning that extends long, lossy, crosstalk-impaired serial links while achieving a bit error rate of 10⁻¹⁵ or less. Each channel locks independently to any rate from 20.2752 to 25.8 Gbps or to supported ÷2 and ÷4 sub-rates, including 10.3125 and 12.5 Gbps, which allows lane-by-lane FEC pass-through; no low-jitter reference clock is needed. [1]

For reach, it combines an adaptive continuous-time linear equaliser (CTLE), an adaptive decision-feedback equaliser (DFE) and a low-jitter transmitter with a 3-tap FIR filter, supporting more than 35 dB of channel loss at 12.9 GHz; transmit amplitude is adjustable from 205 to 1,225 mVppd. It adds an integrated 2 × 2 cross-point, an on-chip eye-opening monitor, a PRBS checker and generator and JTAG boundary scan. Applications listed include front-port optical jitter cleaning, active cables, backplane reach extension, 100GbE (IEEE 802.3bj), InfiniBand EDR, OIF-CEI-25G and SFP28/QSFP28/CFP2/CFP4 ports. [1]

An earlier TI part in the same family, the DS125DF410, shows how retimers are split by rate. Each channel locks independently to 9.8–12.5 Gbps and submultiples, with an adaptive CTLE of up to 34 dB boost at 5 GHz, a self-calibrating 5-tap DFE, CDR and transmit de-emphasis to −15 dB. It lists latency of about 300 ps, 180 mW per channel typical with EQ, DFE, CDR and de-emphasis active, a 2.5 V ±5% supply and a 7 × 7 mm 48-pin WQFN. Its data sheet lists pin-compatible repeater and retimer variants for 8.5–11.3 Gbps and 10.3125 Gbps. Applications include SFP+ ports, backplanes, 10 GbE, CPRI, Interlaken and InfiniBand. [2]

Editorial note: specify the channel loss at the Nyquist frequency of your highest line rate and the BER target, so the supplier can confirm equalisation margin rather than quoting the maximum loss alone. [1]

Give the supplier the line rates and protocols, channel loss at Nyquist and crosstalk, BER target, number of lanes, reference-clock availability, latency budget, FEC needs, cross-point or fan-out needs, power and supply budget, management interface, package and temperature range, and quantity.

02

Check jitter tolerance, loop bandwidth, latency, power and lock

The DS250DF410 lists CDR PLL bandwidth of 5.3 MHz at 10.3125 Gbps and 5.5 MHz at 25.78125 Gbps, and input jitter tolerance at 25.78125 Gbps (30 dB channel, PRBS31, BER < 10⁻¹²) of 9 UIpp at 190 kHz, 1 UIpp at 940 kHz and 0.3 UIpp above 15 MHz. Latency is under 500 ps at 25.78125 Gbps. [1]

The OIF CEI implementation agreement (OIF-CEI-04.0, electrical and jitter interoperability agreements for 6G+ to 56G+ bps I/O) explains what the CDR does to jitter. Low-frequency deviations are tracked by the clock recovery circuit and do not directly affect timing within a bit interval, while untracked jitter does. Jitter generation is jitter appearing at the output with no input jitter applied. Jitter transfer is the ratio of output to input jitter, where a negative dB value means the element removed jitter. For measurement it defines a 'golden PLL' reference clock extractor; where its tracking bandwidth is not otherwise defined, the corner frequency is baud/1667 with a 20 dB/decade roll-off and less than 0.1 dB peaking. [3]

Editorial calculation: at 25.78125 GBd, baud/1667 is about 15.5 MHz. The same agreement states a data-path target bit error ratio below 10⁻¹⁵ per lane, with testing to verify 10⁻¹² per lane. [3]

It runs from a single 2.5 V ±5% supply, with power of 241 mW typical (305 mW maximum) per active channel with CTLE, full DFE, transmit FIR, driver and cross-point enabled, over −40 to +85 °C ambient, in a 6 × 6 mm BGA. It specifies a stay-in-lock range for temperature ramps after initial lock, with conditions stated for airflow and board layers. [1]

Editorial calculation: at 25.78125 Gbps one unit interval is about 38.8 ps, so 0.3 UIpp of high-frequency jitter tolerance is about 11.6 ps; four active channels at 241 mW typical draw about 0.96 W. [1]

03

Compare power on an energy-per-bit basis

Retimer datasheets quote power per channel with a stated feature set; published CDR research quotes energy per bit for the CDR core. Two papers from National Taiwan University give reference points. A 20 Gb/s digital CDR with a one-tap speculative DFE, built in 40 nm CMOS on a 0.1 mm² active area, reached a measured bit error rate below 10⁻¹² over a channel with −10.31 dB loss at 10 GHz using a PRBS 2⁷−1 pattern, drew 55.4 mW at 20 Gb/s (2.77 pJ/b), and its calibration circuit, which improves high-frequency jitter tolerance, converged in under 5 µs. [4]

A second design added a background loop gain controller to raise jitter tolerance. In 40 nm CMOS on 0.0324 mm², it consumed 12.67 mW from a 1 V supply; at 1 Gb/s and 3 Gb/s with PRBS 2¹⁵−1 and BER below 10⁻¹², the retimed data showed 12.3 ps and 7.74 ps rms jitter, and the minimum high-frequency jitter tolerance at 3 Gb/s rose to 0.68 UIpp. [5]

Editorial calculation: the DS250DF410's 241 mW typical per channel at 25.78125 Gbps is about 9.3 pJ/b, but that figure includes CTLE, full DFE, transmit FIR, output driver and cross-point, while the 2.77 pJ/b research figure covers a CDR with a one-tap DFE over a −10.31 dB channel; the DS250DF410 is specified for more than 35 dB of loss at 12.9 GHz. Compare suppliers only with the same blocks enabled, the same channel loss and the same test pattern, since PRBS 2⁷−1 is a far shorter pattern than the PRBS31 used in the DS250DF410 jitter-tolerance test. [1] [4]

04

Find suppliers

The companies in the manufacturer list below show this product on their own websites. Confirm the legal seller, factory and scope for your order.

Ask any supplier for jitter-tolerance and loss-reach data at your line rate and channel, and for power per channel with your feature set enabled. [1]

05

Trace what each block controls

This is a functional reference built from the sources cited; it is not one maker's specification.

06

Fill the specification fields with values for your link

A CDR quotation needs values for your link. The table explains each field, gives published values where a reviewed source states them, and says what to obtain from the supplier.

07

Send the rate, channel and system data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Rates: [Gbps; protocols]
Channel: [loss at Nyquist; crosstalk]
BER: [target]
Lanes: [count; cross-point]
Jitter: [JTOL needs]
Latency/power: [ps; mW]
Package/temperature: [package; range]
Quantity: [units]

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