Clock buffer / driver

01

Set the fan-out, skew and output drive

Texas Instruments' LMK1C110x data sheet describes a family of 1:2, 1:3 and 1:4 LVCMOS clock buffers for 3.3, 2.5 or 1.8 V supplies, with output skew below 50 ps, propagation delay below 3 ns and maximum frequency of 250 MHz at 3.3 V or 200 MHz at 2.5 and 1.8 V, over −40 to 125 °C. At 3.3 V it lists output-to-output skew of 25 ps typical and 50 ps maximum, part-to-part skew of 250 ps, propagation delay of 1.5 to 2 ns, rise and fall times of 0.35 to 0.7 ns into 5 pF, output duty cycle of 45–55 % with a 50 % input, and an output impedance of 50 Ω. TI advises matching the output driver's characteristic impedance to that of the transmission line for best signal integrity. [1]

The same data sheet describes a synchronous output enable that drives the outputs low, unused outputs that can be left floating, and fail-safe inputs that can be driven before the supply is applied and prevent output oscillation with no input signal. [1]

Editorial note: output-to-output skew applies within one buffer; if clocks for one interface come from two buffers, budget for part-to-part skew instead, which this data sheet lists as 250 ps against 50 ps.

Renesas' 5PB11xx family (data sheet dated September 2026) covers wider fan-outs: 1:2, 1:4, 1:6, 1:8 and 1:10 LVCMOS buffers for 1.8–3.3 V with a 3.3 V-tolerant input, 200 MHz maximum frequency, integrated series termination for 50 Ω lines and a synchronous glitch-free output enable. At 1.8 V it lists propagation delay of 1.5–2.5 ns and output-to-output skew of 35 ps typical and 50 ps maximum for the 1:2 and 1:4 parts (58 ps for 1:6), with temperature grades of −40 to +85 °C, −40 to +105 °C and AEC-Q100 automotive grades up to −40 to +125 °C; the automotive 1:4 part allows 200 ps device-to-device skew. [3]

A zero delay buffer adds an on-chip PLL that locks the outputs to the input clock. Infineon's product page for the CY2305SXC-1, which it lists as end of life, describes a 3.3 V zero delay buffer with five LVCMOS outputs for 10 to 133 MHz, a 3.0 to 3.6 V supply and 0 to 70 °C, with output-to-output skew of 85 ps typical, device-to-device skew below 700 ps, 60 ps typical cycle-to-cycle jitter and a duty cycle of 40–60 % at 66.67 MHz. [4] Editorial note: the PLL sets a 10 MHz lower frequency limit that the non-PLL TI and Renesas buffers above do not list, and its jitter is quoted cycle-to-cycle in picoseconds rather than as additive RMS jitter in femtoseconds, so the two figures cannot be compared directly.

Give the supplier the input clock frequency, logic standard and amplitude or slew rate, number of outputs and their standards (LVCMOS, LVDS, LVPECL, HCSL), supply voltage, skew budget, additive jitter limit with integration range, load and trace impedance, output enable or input mux needs, package, temperature range and qualification (industrial or automotive).

02

Budget the jitter the buffer adds

The LMK1C110x data sheet lists additive jitter of 8 fs RMS typical and 20 fs maximum at 3.3 V, measured at 156.25 MHz with a 2 V/ns input slew rate over a 12 kHz to 20 MHz integration range; its feature list gives 7.5 fs typical at 3.3 V, 10 fs at 2.5 V and 19.2 fs at 1.8 V. [1] A Texas Instruments Analog Applications Journal article on clock jitter combines independent jitter components (the clock input's jitter and the ADC's aperture jitter) as the square root of the sum of their squares, and gives the jitter-limited SNR of a sampled signal as SNR = −20 log(2π × f_IN × t_jitter). [2]

Editorial calculation: treating a buffer's additive jitter as an independent term in the same way, a 100 fs RMS reference passed through a buffer adding 20 fs gives √(100² + 20²) ≈ 102 fs. For a 100 MHz input signal the jitter-limited SNR falls from about 84.0 dB to about 83.9 dB. Reference jitter and signal frequency are assumed examples; compare additive jitter only over the same integration range and input slew rate, since the data sheet specifies both.

Renesas gives additive phase jitter below 50 fs RMS (156.25 MHz, 12 kHz–20 MHz) for its industrial grades and up to 60–68 fs for the automotive parts. In its phase-noise example the reference measured about 58.9 fs and the buffer output about 70.9 fs, which it reports as about 39 fs additive. [3]

Editorial calculation: the Renesas example follows the root-sum-square rule, √(70.9² − 58.9²) ≈ 39.5 fs; the same rule shows why a 50 fs buffer barely changes a 200 fs reference (√(200² + 50²) ≈ 206 fs) but matters more for a 60 fs one (≈ 78 fs). [3]

03

Compare what suppliers offer

Suppliers linked to this page list clock buffers; each card links to the page reviewed.

Listings include differential and single-ended clock buffers alongside crystal oscillators and clock generators, clock buffers with time servers and clock chips, and clock buffer and driver ICs in a component distributor's catalogue. Ask each for the data sheet with skew, additive jitter and its measurement conditions.

04

Trace the buffer functions

This is a functional reference built from the sources cited; it is not one maker's specification.

05

Fill the specification fields with values for your board

A clock buffer quotation needs values for your design. The table explains each field, gives published values where a reviewed source states them, and says what to obtain from the supplier.

06

Send the clock, output and timing data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Input: [frequency; standard; amplitude/slew rate]
Outputs: [number; standards; loads]
Timing: [skew budget; additive jitter limit; integration range]
Supply: [voltage]
Features: [output enable; input mux; fail-safe]
Package: [type; temperature; qualification]
Quantity: [volume; reel]

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