Field-programmable gate array (FPGA)

01

Count logic resources by architecture

Xilinx's 7 Series FPGAs Configurable Logic Block user guide describes CLBs as the main logic resources for sequential and combinational circuits, each connected to a switch matrix for the general routing. A 7 Series LUT can be a 6-input LUT with one output or two 5-input LUTs with shared inputs; four 6-input LUTs, their eight flip-flops, multiplexers and carry logic form a slice, and two slices form a CLB. About two-thirds of slices are SLICEL logic slices; the rest are SLICEM, whose LUTs can also serve as 64-bit distributed RAM or 32-bit shift registers (SRL32). Dedicated carry logic speeds arithmetic. [1]

Lattice describes its iCE40 UltraPlus family as having 2,800 or 5,280 four-input LUTs. [2]

Efinix counts its Trion devices, built on a 40 nm process, in logic elements (LEs): 3,888 in the T4, 19,728 in the T20 and 112,128 in the T120, a stated range of 4K to 120K LEs. [3] Editorial note: LEs, four-input LUTs and six-input LUT slices are each maker's own units, which is one more reason to compare families by synthesis results.

Editorial calculation: one 7 Series CLB holds 2 × 4 = 8 six-input LUTs and 2 × 8 = 16 flip-flops; one SLICEM used as distributed RAM gives 4 × 64 = 256 bits. Because a 6-input LUT can implement larger functions than a 4-input LUT, LUT counts are not directly comparable between families; compare by synthesising your design for each candidate.

Give the supplier or distributor the target family or required resources (LUTs, flip-flops, block RAM, DSP), I/O count and standards, high-speed serial needs, clocking, configuration memory and security, power budget, package and pitch, temperature grade and qualification, toolchain and IP licensing, longevity and supply commitments.

02

Match memory, DSP, power and package

Lattice lists for the iCE40 UltraPlus up to 80 kbit of embedded dual-port memory and 1 Mbit of embedded single-port memory, DSP blocks with multiply-accumulate functions, static current as low as 75 µA with 1–10 mA active current in the applications Lattice targets, and packages from a 2.15 × 2.50 mm WLCSP to a 0.5 mm pitch 7 × 7 mm QFN, aimed at always-on edge and IoT uses. [2] Xilinx's guide notes that SLICEM distributed RAM and shift registers add memory inside the logic fabric, alongside wide multiplexers and dedicated carry chains. [1]

Efinix lists its Trion family with 77 kb to 5,407 kb of embedded RAM in 15 to 1,056 5K RAM blocks, 4 to 320 18 × 18 multipliers, and 1 to 8 PLLs, and packages from a 49-ball FBGA of 3 × 3 mm at 0.4 mm pitch and an 80-ball WLCSP of 4.5 × 3.6 mm to a 256-ball FBGA of 13 × 13 mm at 0.8 mm pitch. Its 100-pin LQFP100F3 package includes 16 Mbit of SPI flash that can store multiple configuration bitstreams, and Efinix states it intends to support the Trion family in customer designs until at least 2045. [3]

Editorial calculation: 5,407 kb across 1,056 blocks is about 5.1 kb per block, consistent with the 5K block size; the 3 × 3 mm FBGA covers 9 mm² against 5.4 mm² for Lattice's 2.15 × 2.50 mm WLCSP. [3] [2]

Editorial note: memory figures from different families mix distributed (in-LUT) and block memory; list each type separately in your requirement, and check package pitch against your PCB process before choosing the smallest package.

03

Compare FPGA families

No manufacturer record has been reviewed for this product yet; the families below come from the sources cited.

Examples range from small low-power families with four-input LUTs, kilobit-to-megabit embedded memory and wafer-level packages to larger families with six-input LUT slices, distributed RAM and dedicated carry chains, and families of up to 120K logic elements with hardened MIPI CSI-2 and DDR DRAM controllers. [2] [1] [3]

04

Check configuration memory, supply rails and sleep current

Renesas lists its SLG47910V ForgeFPGA with 1,120 six-input, two-output LUTs, 1,120 D flip-flops, 5 kb of distributed memory and 32 kb of block RAM, a 50 MHz on-chip oscillator and one PLL. A design is created by programming one-time programmable (OTP) non-volatile memory, and the parameter table also lists SPI controller and SPI target configuration modes; CRC bitstream checking applies to OTP configuration only. [4]

Supplies are VDDIO 1.71–3.465 V and VDDC 1.1 V ±5%, with 19 GPIOs in the QFN package, operation from −40 to +85 °C, 14 µA in sleep or reset mode and 52 µA static Iddc. Packages are a 24-pin STQFN of 3.0 × 3.0 mm at 0.4 mm pitch and a 20-lead WLCSP of 1.85 × 1.64 mm at 0.35 mm pitch. [4]

Editorial calculation: the WLCSP covers 1.85 × 1.64 ≈ 3.0 mm² against 9.0 mm² for the QFN. Editorial note: an OTP-configured part cannot have its logic rewritten in the field, so state in the enquiry whether the product needs in-field updates from SPI flash. [4]

05

Trace the device resources

This is a functional reference built from the sources cited; it is not one maker's specification.

06

Fill the specification fields with values for your design

An FPGA quotation needs values for your design. The table explains each field, gives published values where a reviewed source states them, and says what to obtain from the supplier.

07

Send the design, power and package data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Design: [LUTs; flip-flops; RAM; DSP; clock rates]
I/O: [count; standards; serial links]
Power: [budget; supply rails]
Package: [type; pitch; size]
Grade: [temperature; qualification]
Supply: [volume; longevity; toolchain/IP]

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