Ethernet PHY chip (physical-layer transceiver IC)

01

Match speeds, media and the MAC interface

TI's DP83867 datasheet describes a 10/100/1000 Mbps Ethernet PHY with integrated PMD sublayers for 10BASE-Te, 100BASE-TX and 1000BASE-T, fully compatible with IEEE 802.3, connecting to twisted-pair media through an external transformer and to the MAC through MII, GMII or RGMII; the 64-pin QFP supports all three and the 48-pin QFN supports RGMII. It lists 16 programmable RGMII delay modes, programmable MII/GMII/RGMII termination impedance, integrated MDI termination resistors, configurable I/O voltage of 3.3, 2.5 or 1.8 V, a 25 MHz crystal or oscillator reference, a 25 or 125 MHz synchronised clock output, RJ45 mirror mode and JTAG. [1]

Its applications include motor drives, factory automation, fieldbus support, industrial embedded computing, communications infrastructure, test and measurement and consumer electronics; it supports up to 130 m of cable and offers cable diagnostics and dynamic link-quality monitoring for fault prediction. [1]

For 10/100 Mbps links, TI's DP83826 is an industrial PHY for 10BASE-Te and 100BASE-TX with MII or RMII MAC interfaces, a single 3.3 V supply with 1.8 V or 3.3 V I/O, cable reach above 150 m, EtherCAT compliance and an RMII back-to-back repeater mode; TI's DP83848 family is a 10/100 PHY with MII, RMII or SNI interfaces, Auto-MDIX, auto-negotiation, error-free operation up to 150 m and a 48-pin package. [2] [3]

Editorial note: confirm the MAC on your processor or FPGA offers the same interface (RGMII on the QFN part) and I/O voltage, and whether the PHY or the MAC adds the RGMII clock delay. [1]

Give the supplier the speeds and media, MAC interface and I/O voltage, latency and IEEE 1588/TSN needs, ESD and EMC targets, power budget and available supplies, cable length, package, temperature grade, Wake-on-LAN or diagnostics features and quantity.

02

Check latency, time sync, robustness and power

The DP83867 lists RGMII latency below 90 ns on transmit and below 290 ns on receive, Time Sensitive Network compliance, start-of-frame detection for IEEE 1588 timestamps and a fast link-drop mode; it exceeds 8,000 V IEC 61000-4-2 ESD (direct contact) and meets EN 55011 class B emissions. [1]

It consumes 490 mW in the 64-pin QFP (PAP) and 457 mW in the 48-pin QFN (RGZ) at full operating power, with Wake-on-LAN packet detection to cut system power; analogue supplies are 2.5 V (±5%) and 1.0 V. The IR versions are rated −40 to 85 °C (12 × 12 mm QFP or 7 × 7 mm QFN) and the CR version 0 to 70 °C. [1]

The DP83826 lists deterministic latency of 40 ns transmit and 170 ns receive, varying by under ±2 ns over power cycles, fast link-drop under 10 µs, IEC 61000-4-2 ESD of ±8 kV contact and ±15 kV air, IEC 61000-4-4 EFT of ±4 kV, CISPR 22 class B conducted and radiated emissions, power under 160 mW, Energy Efficient Ethernet and Wake-on-LAN, and −40 to 105 °C (E version) or −40 to 85 °C (I version). The DP83848 lists under 270 mW typical power, a 25 MHz clock output and versions specified from −40 °C to 105 °C. [2] [3]

Editorial calculation: across one 100 Mbps link of two DP83826s, PHY latency is about 40 + 170 = 210 ns, compared with under 380 ns for two gigabit DP83867s. [2] [1]

Editorial calculation: a frame crossing one link passes the transmit PHY at one end and the receive PHY at the other, so the two DP83867s add under 90 + 290 = 380 ns of PHY latency, before cable propagation and the MACs. [1]

03

Compare what suppliers offer

The companies in the manufacturer list below show this product on their own websites. Confirm the legal seller, factory and scope for your order.

The reviewed data sheets cover a gigabit PHY with RGMII/GMII and IEEE 1588 support (DP83867), a deterministic-latency 10/100 industrial PHY for real-time fieldbuses (DP83826), and a general 10/100 PHY with MII, RMII or SNI for embedded and automotive use (DP83848). [1] [2] [3]

Ask each supplier for speed support, MAC interface options, latency, ESD and EMC results, cable reach, power, temperature grade and package. [1]

04

Check a 2.5G PHY's serial MAC link, idle power and temperature grade

MaxLinear's page for its GPY211 describes a single-port 2.5 Gbit/s Ethernet PHY supporting the 2.5GBASE-T, 1000BASE-T, 100BASE-TX and 10BASE-Te modes of IEEE 802.3. It connects to the MAC of an SoC or switch through an SGMII+/SGMII interface; SGMII+ runs at 3.125 Gbaud/s to carry 2.5 Gbit/s, and rate adaptation uses IEEE 802.3x pause frames. It supports IEEE 1588v2 time stamping and Energy-Efficient Ethernet in the 2.5GBASE-T, 1000BASE-T and 100BASE-TX modes. [4]

The page also lists cable diagnostics, automatic down-speed on Cat3 (four-wire) or bad cables, auto MDI/MDI-X, Wake-on-LAN, a programmable temperature sensor for warning and down-speed, and pin compatibility with MaxLinear's GPY212, GPY215 and GPY115. [4]

Editorial note: unlike the parallel MII/GMII/RGMII interfaces of the DP83867 above, this PHY needs a SerDes port on the MAC that runs SGMII or SGMII+, and its 0 to 70 °C rating is narrower than the DP83867IR's −40 to 85 °C; confirm both before choosing a 2.5G part. [4] [1]

05

Trace what each block controls

This is a functional reference built from the source cited; it is not a full specification.

06

Fill the specification fields with values for your board

An Ethernet PHY quotation needs values for your board. The table explains each field, gives published values where the reviewed source states them, and says what to obtain from the supplier.

07

Send the link, interface and board data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Speeds/media: [10/100/1000BASE-T]
MAC interface: [MII; GMII; RGMII; I/O V]
Timing: [latency; 1588; TSN]
Robustness: [ESD; EMC]
Power/supplies: [mW; rails]
Cable: [m]
Package/grade: [QFN/QFP; °C]
Quantity: [units]

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