Programmable gain amplifier (PGA)

01

Pick the gain steps and channels

TI's PGA112/PGA113/PGA116/PGA117 data sheet describes zero-drift PGAs with binary gains of 1, 2, 4, 8, 16, 32, 64 and 128 (PGA112, PGA116) or scope gains of 1, 2, 5, 10, 20, 50, 100 and 200 (PGA113, PGA117), a 2-channel (10-pin VSSOP) or 10-channel (20-pin TSSOP) input MUX, a three-pin SPI interface, four internal calibration channels (GND, 0.9 VCAL, 0.1 VCAL and VREF), 200 ns gain switching time, rail-to-rail input and output, and an output optimised for driving capacitive-DAC ADCs. [1] Microchip's MCP6S21/2/6/8 offer 1, 2, 6 or 8 multiplexed inputs and gains of +1, +2, +4, +5, +8, +10, +16 or +32 V/V selected over SPI, on a single 2.5–5.5 V supply, with 2–12 MHz bandwidth marked “typ” and shutdown via the serial interface. [3]

Editorial calculation: assuming an ideal zero-offset, noninverting gain stage, a unipolar 20 mV input and a 0–2.5 V ADC range, 0.020 × 64 = 1.28 V, 0.020 × 128 = 2.56 V and 0.020 × 100 = 2.0 V. The nominal 128 setting exceeds that assumed ADC range. The nominal ratio 128/1 corresponds to 20 log₁₀(128) ≈ 42.14 dB. These are editorial calculations, not manufacturer-published operating measurements or a completed gain selection; allow actual reference level, headroom, offset, gain error and transients before selecting hardware. [1]

Give the supplier the signal ranges per channel, number of channels, gain steps needed (binary or decade), ADC input range and type, supply voltages, interface (SPI, daisy-chain, GPIO), gain error, offset and drift limits, noise, bandwidth and settling time after gain changes, input voltage range and protection, package and temperature range.

02

Check accuracy, drift and input range

Under the PGA112 family’s stated 5 V, 25°C and mid-supply common-mode conditions, offset is ±25 µV in the “TYP” column and ±100 µV maximum. Its −40 to +125°C, 2.5 V common-mode drift entries are 0.35 µV/°C in “TYP” and 1.2 µV/°C maximum; different common-mode and temperature conditions have different entries. Gain error is 0.1% maximum at G ≤ 32 and 0.3% at the higher listed gains, within the stated output range. Its 12 nV/√Hz noise-density entry is in “TYP” at 5 V and above 10 kHz. [1] Microchip’s MCP6S2x headline values are ±1% maximum gain error, ±275 µV maximum offset and 10 nV/√Hz at 10 kHz marked “typ”, with the stated −40 to +85°C specification range. [3] TI’s PGA280 headline input range is ±15.5 V on ±18 V supplies. Its gain-128 offset table gives ±3 µV in “TYP” and ±15 µV maximum under its stated test conditions. It also provides differential output, input switching, overload detection and wire-break test current; check the detailed limits rather than treating its headline CMRR as a guarantee under every condition. [2]

Editorial note: check the total error from gain error and offset at the gain you will actually use, and allow the settling time after each gain change before the ADC samples.

03

Separate a standalone PGA from an MCU analog front end

The standalone TI and Microchip parts leave converter selection outside the PGA; Renesas’s identified MCU integrates its analog front end. [1] [3] [4]

Types include low-voltage rail-to-rail PGAs with integrated MUX for ADC driving, and high-voltage programmable-gain instrumentation amplifiers with differential output and diagnostics for industrial analog input modules. [1] [3] [2]

04

Consider a PGA built into a delta-sigma ADC front end

Renesas’s RX23E-A datasheet Rev.1.30, dated 25 December 2024, describes integrated delta-sigma ADCs and PGA gains from 1 to 128. Its up-to-23-bit effective-resolution headline is at gain 1 and 7.6 SPS, not at every gain and rate. Normal-mode output rates are 7.6–15625 SPS, while low-power mode is 1.9–3906 SPS. The device’s VCC range starts at 1.8 V, but the delta-sigma analog supply AVCC0 is 2.7–5.5 V; the lower analog-supply exception applies only when S12AD operates. Do not carry the MCU VCC minimum over to the delta-sigma PGA front end. [5]

In the cited Renesas electrical table, offset drift at PGA gains 64–128 is 10 nV/°C in “Typ.” and 25 nV/°C maximum. Lower gains have different entries. Gain drift with the PGA enabled and OPCR.DSADLVM = 0 is 1 ppm/°C in “Typ.” and 3 ppm/°C maximum; other modes and supplies have different limits. This replaces an unqualified drift comparison based on a product-page summary. [5]

The Renesas product page identifies an MCU with an analog front end; use its linked datasheet conditions for quantitative selection. Compare noise, effective resolution, reference conditions and settling at the gain and data rate used. [4] [5]

05

Track channel selection, gain and reference paths

The gain code alone does not identify the input channel, reference level or output-settling condition.

06

Specify analog settling separately from gain-code switching

Record the allowed error band, output step and load when asking for settling time.

07

Send the signal, ADC and interface data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Signals: [ranges; channels; bandwidth]
Gain: [steps; switching rate]
Accuracy: [gain error; offset; drift; noise]
ADC: [type; input range]
Supply: [rails]
Interface: [SPI; daisy-chain]
Package: [type; temperature]

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