Analog-to-digital converter (ADC) chip

01

Choose the architecture, resolution and sample rate

TI describes its ADS8681 as a successive-approximation (SAR) ADC data-acquisition system: a 16-bit converter at up to 1 MSPS (500 kSPS for ADS8685, 100 kSPS for ADS8689) with an integrated analog front end, overvoltage protection to ±20 V and an on-chip 4.096 V low-drift reference, aimed at analog input modules, semiconductor test and servo drive control. [1]

TI describes its ADS1262 as a precision 32-bit delta-sigma (ΔΣ) ADC with data rates from 2.5 SPS to 38,400 SPS, a CMOS PGA with gains 1 to 32, a ΔΣ modulator and a programmable digital filter, two sensor-excitation current sources for RTDs, and 11 multifunction inputs, aimed at weigh scales, strain gauges, thermocouples and RTDs in factory automation and instrumentation. [2]

Editorial note: the two parts show the trade-off — the SAR converter samples at up to 1 MSPS at 16 bits, the ΔΣ converter resolves 32 bits at up to 38.4 kSPS with line-frequency rejection; choose from your bandwidth and noise needs rather than from the bit count alone. [1] [2]

Measured silicon shows how SNDR, ENOB and power trade off inside a SAR converter. A Sungkyunkwan University 12-bit, 20 MS/s asynchronous SAR ADC in 65 nm CMOS (0.14 mm² active area) reached 65.44 dB SNDR at the Nyquist input while drawing 472.2 µW from a 1 V supply; it measured an ENOB of 10.98 bits at a 4 MHz input and 10.58 bits near Nyquist, peak DNL of ±0.6 LSB and INL of ±0.9 LSB, and a figure of merit of 15.42 fJ per conversion step. [4]

Editorial calculation: ENOB = (SNDR − 1.76) ÷ 6.02 = (65.44 − 1.76) ÷ 6.02 ≈ 10.58 bits, so the 12-bit converter delivers about 1.4 bits less than its nominal resolution at Nyquist; the Walden figure of merit P ÷ (fs × 2^ENOB) = 472.2 µW ÷ (20 MS/s × 2^10.58) ≈ 15.4 fJ per step, matching the paper. Apply the same two checks to any datasheet: compare SNDR-derived ENOB at your input frequency, not the nominal bit count. [4]

Give the supplier the signal type and full-scale range, bandwidth and sample rate, number of channels and multiplexing, resolution and required SNR, INL and drift, reference (internal or external) and its drift, input impedance and protection, interface (SPI, parallel, LVDS), supply rails and power budget, temperature range, package, and quantity.

02

Check input range, accuracy, reference, interface and power

The ADS8681 offers software-programmable bipolar ranges of ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V and ±2.56 V and unipolar ranges up to 0–12.288 V from a single 5 V supply, with constant resistive input impedance of at least 1 MΩ. It lists DNL of ±0.4 LSB, INL of ±0.5 LSB, SNR of 92 dB and THD of −107 dB, a multiSPI interface with daisy-chain, 8.2 mA (typ.) analog supply current at 1 MSPS with the internal reference, operation from −40 to +125 °C, and 16-pin TSSOP or 4 × 4 mm WQFN packages. [1]

The ADS1262 lists offset drift of 1 nV/°C, gain drift of 0.5 ppm/°C, noise of 7 nV rms at 2.5 SPS and gain 32, linearity of 3 ppm, a 2.5 V internal reference with 2 ppm/°C drift, 130 dB rejection of 50 and 60 Hz, single-cycle settled conversions, internal fault monitors and a 28-pin TSSOP package over −40 to +125 °C. [2]

Editorial calculation: 92 dB SNR corresponds to an effective resolution of (92 − 1.76) ÷ 6.02 ≈ 15.0 bits; on the ±10.24 V range one 16-bit LSB is 20.48 V ÷ 65,536 ≈ 312.5 µV; and 8.2 mA at 5 V is about 41 mW. [1]

03

Consider low-power sensor ADCs with built-in PGA and reference

SGMICRO's SGM51610S is a 16-bit sensor ADC with a programmable gain amplifier giving input ranges from ±256 mV to ±6.144 V, an input multiplexer for four single-ended or two differential inputs, an internal oscillator, low-drift reference and temperature sensor, and an SPI-compatible interface, in MSOP-10 or 2 × 1.5 mm UTQFN-10 packages for −40 to +125 °C. Its maker lists battery current measurement, BMS insulation detection, thermocouple measurement with cold-junction compensation and thermistor measurement among applications. [3]

This sits at the opposite end from the 1 MSPS SAR data-acquisition ADC and the 32-bit precision delta-sigma converter above: low rate and low power, with the PGA, reference and multiplexer integrated for slow sensor signals. [3] [1] [2]

Editorial calculation: at 16 bits the code step on the ±256 mV range is 512 mV / 65,536 ≈ 7.8 µV, and on the ±6.144 V range about 188 µV.

State the sensor type and signal span, required sample rate, supply and current budget, and ask for noise-free resolution at your data rate and range, reference drift and line-rejection settings.

04

3PEAK's SAR converter and SG Micro's ADC range

Ask any supplier for the datasheet with SNR, INL and drift over temperature at your sample rate and range, and for evaluation-board data. [1] [2]

05

Front end, converter core, filter and reference: where accuracy is set

The reference row sets absolute accuracy and drift whichever converter core is chosen, so state an internal or external reference in the order. [1] [2]

06

Bits, rate, range and noise to request on the chip datasheet

Read the resolution row against measured ENOB: the 12-bit SAR in the Sungkyunkwan paper delivers about 10.58 effective bits near Nyquist. [4]

07

Send the signal, accuracy and system data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Signal: [range; bandwidth; channels]
Architecture: [SAR; ΔΣ]
Accuracy: [SNR; INL; drift]
Reference: [internal; external]
Interface: [SPI; other]
Power: [rails; mW]
Package/temperature: [package; range]
Quantity: [units]

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