Application-specific integrated circuits (ASICs)

01

Understand what the one-time cost (NRE) covers

AnySilicon, an ASIC industry information site, describes non-recurring engineering (NRE) as the cost of turning requirements into manufacturable silicon and breaks it into a stack: engineering effort (architecture, RTL, physical design, signoff); verification (testbenches, coverage, regressions and closure); IP licensing (interface IP, memories, PLLs, SerDes, security blocks); tapeout preparation (checks, documentation, coordination); manufacturing setup (masks and engineering wafers); and test development (patterns, characterisation and production strategy). It names verification as the cost first-time ASIC teams underestimate more than any other, since every new interface, operating mode, power state or corner case multiplies the verification matrix. Proven IP can save months but still needs integration and verification, mask costs are real but only one part of the total, aggressive process nodes improve density and power while adding complexity, and multi-project wafer (MPW) runs can reduce early cost but are not always the right route to production. [1]

Editorial note: ask suppliers to quote NRE line by line in these categories, stating the node, IP list and verification scope assumed, so that quotes can be compared and changes priced. [1]

Give the supplier the functions and interfaces, analog and digital content, performance, power budget, supply voltage, target process node, IP needed, package type, size and I/O count, operating temperature and qualification (e.g. automotive), ESD requirements, annual volume and product lifetime, prototype route (MPW or dedicated masks), test and yield expectations, who owns the design and masks, and schedule.

02

Check whether volume and lifetime repay the NRE

AnySilicon's break-even guide compares FPGA and ASIC economics: an FPGA's cost includes not only device price but higher power — affecting batteries, thermal design and enclosures — and larger boards with more components, costs repeated on every unit; an ASIC moves much of the cost up front into NRE. The question is whether NRE can be amortised across enough units over a long enough life. As starting points rather than rules, it suggests that below about 10,000 units a year FPGA wins on flexibility and speed, 10,000–50,000 is ambiguous, 50,000–200,000 is where ASIC starts to make economic sense, and above 200,000 ASIC economics are compelling if the specification is stable; severe power constraints and integration pressure pull the break-even point earlier. [2]

Editorial calculation: with assumed figures — USD 2 million NRE and a saving of USD 20 per unit against an FPGA design — break-even is 2,000,000 ÷ 20 = 100,000 units, or two years at 50,000 units a year; halve the per-unit saving and the break-even doubles to 200,000 units. Use your own NRE quote and unit-cost estimates. [2]

03

Price a prototype run on a multi-project wafer

EUROPRACTICE publishes its 2026 multi-project wafer (MPW) and mini@sic run schedules and prices by foundry and process. For TSMC mini@sic runs it lists a standard price for a minimum area plus a price per extra 0.1 mm²; for other runs, such as ams OSRAM and X-FAB, a price per mm² with a minimum fabrication cost. Discounted prices apply only to academic and research customers in listed countries who are paid-up members and whose designs serve education or publicly funded research; standard prices apply to all other customers. [4]

Older and specialty processes are priced by area: ams OSRAM 0.35µ CMOS C35B4C3 at 640 EUR/mm² and 0.18µ CMOS at 1,650 EUR/mm² (standard), and X-FAB XH018 0.18µ CMOS E-FLASH at 1,126–1,314 EUR/mm² by metal stack, each with a minimum chargeable area set in footnotes [4]. AnySilicon notes that MPW runs can reduce early cost but are not always the right route to production [1]; use these prices to size the prototype step, then ask the design house for the production mask cost separately.

The run calendar is part of the schedule risk: each process has fixed tape-out dates in the year, for example ams OSRAM 0.35µ C35B4C3 runs listed in March, July and November 2026 [4]. Ask the supplier which run date its schedule assumes and what happens to the plan if verification misses it.

Editorial calculation: a 2 mm² die on TSMC 28 HPC+ RF would cost 10,609 + 10 × 919.19 ≈ 19,800 EUR at standard price, and on TSMC 65 LP MS RF 4,491 + 10 × 419 = 8,681 EUR, before packaging and test. [4]

Values are from EUROPRACTICE's 2026 schedules and prices page; prices are for prototype runs, exclude packaging and test, and can change.

04

Compare what suppliers offer

The manufacturer card below states what the reviewed source shows.

When requesting quotations, ask each design house or foundry partner for a line-by-line NRE breakdown, the node and IP proposed, verification plan, MPW and production schedule, and unit price at your volumes.

05

Weigh the area, speed and power gap against an FPGA

Researchers at the University of Toronto measured the same benchmark circuits on a 90 nm CMOS SRAM-programmable FPGA and in 90 nm CMOS standard-cell ASICs. For circuits built only from logic and flip-flops, the FPGA needed on average 40 times the silicon area, was 3.2 times slower and used 12 times more dynamic power than the standard-cell implementation. [3] When the FPGA designs used hard multiplier-accumulator and memory blocks, the area gap fell to 28 times (multipliers), 37 times (memories) and 21 times (both), and the dynamic power gap to 12, 9.2 and 9.0 times, while the delay gap changed little. [3]

The authors report static power with a caveat: logic-only FPGA designs drew 87 times more static power than the ASIC for typical silicon at 25 °C, but only 5.4 times under worst-case silicon at 85 °C, and they state that the usefulness of either result is unclear. [3]

Editorial note: these ratios come from one 2006 study at 90 nm; use them to judge whether the unit-cost and power savings behind your break-even case are plausible, and ask the design house for area, speed and power estimates for your own design at the node it proposes. [3]

06

Trace the ASIC project

This is a process reference built from the sources cited; it is not one supplier's flow.

07

Fill the specification fields with values for your project

An ASIC quotation needs values for your project. The table explains each field, gives published values where a reviewed source states them, and says what to obtain from the supplier.

08

Send the functions, volume and constraints together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Function: [blocks; interfaces; analog content]
Targets: [power; voltage; frequency]
Node: [preferred; foundry]
IP: [list]
Package: [type; size; I/O]
Qualification: [temperature; automotive]
Volume: [per year; lifetime]
Route: [MPW prototypes; masks ownership]

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