Image signal processor (ISP) core: the processing core that turns raw Bayer sensor data into frames inside a vision SoC
The image signal processor core inside a vision SoC · the fixed pipeline that takes raw Bayer pixels from a CMOS sensor and hands demosaiced, denoised, tone-mapped frames to the CPU, NPU or encoder, sized by pixels per second, exposures merged and outputs per frame
A CMOS image sensor delivers raw Bayer data: one colour per pixel, defects, lens shading and noise included. Before a neural network, video encoder or inspection algorithm can use it, a dedicated hardware block has to demosaic the pattern, correct defects and shading, reduce noise, merge HDR exposures, map tones and convert colour space, at the full pixel rate of every connected camera. That block is the ISP core. It is designed into an application processor or ASIC, licensed as IP or bought inside a vision SoC, and it decides how many cameras, what resolution and what frame rate a vision product can run.
Image signal processor cores in vision SoCs and ASICs: the raw-Bayer-to-YUV/RGB pipeline, its pixel-rate limits, HDR exposure modes, camera inputs, output paths, statistics for auto-exposure and focus, and dewarp. Custom chip development as a whole is covered on the Application-specific integrated circuits (ASICs) page; the sensor that feeds the ISP on the Image sensor (CMOS image sensor) page; neural accelerators on the Neural processing unit and AI accelerator module pages; DSP chips on the Digital signal processor page; FPGA camera-input boards that do their own Bayer processing on the Processing Board page; and complete vision boxes and computers on the Image processing unit with built-in LED strobe control and Image processing computer for PCB optical inspection pages.
CNFX editorial research · Sources checked October 13, 2026 · 4 sources
Pixels per second set the limit: 12 MP at 30 fps, 4K at 45 fps or 1080p at 120 fps on one i.MX 8M Plus ISP, and what HDR exposures cost
RidgeRun's porting guide for the NXP i.MX 8M Plus, which has two 4-lane MIPI CSI-2 inputs and two ISP instances, tabulates what each ISP can take: [1]
Editorial calculation: 4096 × 3072 × 30 = 377 Mpixel/s and 3848 × 2168 × 45 = 375 Mpixel/s, so the 12 MP and 4K rows describe the same ceiling of roughly 375 million pixels a second; 1936 × 1198 × 120 = 278 Mpixel/s for one ISP, and two ISPs at 80 fps each give 2 × 186 = 371 Mpixel/s together. In each row the two-exposure HDR rate is half and the three-exposure rate a third of the non-HDR rate, which is what follows if every exposure has to pass through the same pixel pipeline. [1]
The same guide notes a separate dewarp engine that corrects lens distortion, with one fisheye lens supported at up to 4K or 12 MP (4096 × 3072) at 30 fps, and warns that the default video driver in ISP sources 4.2.2.16.0 caps width and height at 4K unless the code is changed. [1]
Give the number of cameras, resolution and frame rate of each, and whether any run in HDR and with how many exposures; ask the SoC supplier for the ISP pixel rate with all of them streaming at once.
02
Inside the core: demosaic, defect and shading correction, tone mapping, two output paths and 3A statistics
The i.MX 8M Plus ISP converts raw Bayer to YUV and lists these processing blocks per ISP: Bayer demosaicing and filtering (denoise, sharpen, blur), defect pixel cluster correction, colour processing, chromatic aberration correction, denoise, histogram, lens shading correction, wide dynamic range with local tone mapping, exposure measurement for AE and autofocus measurement, and HDR. [1]
Both Linux drivers expose the ISP as one processing block feeding two separately scaled outputs, so one camera can give a full-resolution stream and a smaller stream at the same time; in the Mali-C55 driver the frame sequence numbers of the two pipes are kept in step even if one is started later. [3][4] Tap points inside the Mali-C55 let data bypass some or all processing steps, which is how RAW output is obtained from the full-resolution pipe. [3]
Arm pitches the C55 at smart cameras and edge AI vision, citing licence-plate detail on vehicles at up to 75 mph, and supplies control software with tuning and calibration tools; Renesas is named as its first public licensee. [2] Editorial note: tuning files are tied to a sensor and lens, so changing either means re-tuning the ISP.
ISP core
Inputs and size
Outputs
Stated limits or claims
Arm Mali-C55 (licensable IP)
Up to 8 separate camera inputs; resolutions up to 8K; maximum image size 48 MP, larger by combining more than one C55 [2]
AXI and AHB interfaces to Cortex-A or Cortex-M SoCs; output can go directly to a machine learning accelerator [2]
About half the silicon area of previous Arm ISP generations; improved tone mapping, spatial noise reduction and HDR sensor support over Mali-C52 [2]
Mali-C55 under Linux
Raw Bayer or RGB/YUV from sensors via a parallel interface or a memory reader; integrated test pattern generator [3]
Full Resolution pipe (can also output RAW) and Downscale pipe, plus a 3A statistics device [3]
Input and output resolutions limited to between 640 × 480 and 8192 × 8192 [3]
Rockchip ISP1 under Linux (RK3288, RK3399 and later revisions)
Ask which processing blocks are in hardware, the output paths and formats, the maximum input and output size, the statistics provided for AE, AWB and AF, the Linux driver status and who supplies tuning for your sensor and lens.
03
What to send for an image signal processor core or ISP-equipped SoC
Paste it into your enquiry below or into an email to a maker, then replace every bracket.
Cameras: [number; sensor model; resolution; frame rate; Bayer bit depth]
HDR: [exposures per frame; line-interleaved or other]
Outputs: [streams per camera; resolutions; formats]
Corrections: [dewarp; lens shading; defect pixels]
Integration: [licensed IP or SoC; bus interface; NPU link]
Software: [Linux driver; tuning tools; calibration for your lens]
Explore company information and manufacturing capabilities, then discuss the scope of your project with a relevant supplier.
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Compiled and source-reviewed by the CNFX editorial team.
Each manufacturer above links to the page on that company's own website where the product is listed, with the date we checked it. How we source and review
· Page last updated 13 October 2026
Buyer questions
How many pixels per second can one i.MX 8M Plus ISP process?
RidgeRun's table gives 12 MP at 30 fps, 4K at 45 fps or 1080p at 120 fps per ISP; by editorial calculation the first two are both about 375 Mpixel/s. [1]
What does HDR cost in ISP throughput?
On the i.MX 8M Plus ISP, two-exposure line-interleaved HDR halves the frame rate and three-exposure HDR cuts it to a third, for example 30, 15 and 10 fps at 12 MP. [1]
How many cameras can an Arm Mali-C55 ISP handle?
Arm states up to eight separate camera inputs, resolutions up to 8K and a maximum image size of 48 MP. [2]
What resolutions does the Linux Mali-C55 driver accept?
The kernel documentation limits ISP input and output to between 640 × 480 and 8192 × 8192. [3]
Sources and what still needs a direct check
Sources checked 2026-10-13. Arm's announcement describes its own ISP; the Linux kernel documentation describes the upstream Mali-C55 and Rockchip ISP1 drivers; RidgeRun's developer wiki summarises the i.MX 8M Plus ISP from NXP's reference manual and porting guide.
