Digital signal processor (DSP chip)

01

Choose the core: fixed or floating point, and how much arithmetic

Texas Instruments describes the TMS320C6748 as a fixed- and floating-point DSP built on a C674x VLIW core at 375 or 456 MHz, rated at up to 3,648 MIPS and 2,746 MFLOPS. The core has 64 general-purpose 32-bit registers, six ALU functional units and two multiply units; it handles 32-bit integer and IEEE single- and double-precision floating point, and per clock it can do two single-precision floating-point multiplies or, in fixed point, two 32 × 32-bit, four 16 × 16-bit or eight 8 × 8-bit multiplies, with hardware support for modulo loops. [1]

At the low-power end, TI's TMS320C5535 family uses a fixed-point C55x core at 50 or 100 MHz (20 or 10 ns instruction cycle) that executes one or two instructions per cycle. Its two multiply-accumulate units each do a 17 × 17-bit multiply and a 32-bit add in a single cycle, for up to 200 million multiply-accumulates per second; a 40-bit ALU is supported by a 16-bit ALU, and the TMS320C5535 adds a tightly coupled FFT accelerator for 8- to 1,024-point real and complex FFTs. TI lists wireless headsets, echo-cancellation headphones, voice applications, portable medical devices and software-defined radio as uses. [2]

Where the DSP is to be built into a customer's own chip, the core is licensed as intellectual property rather than bought as a packaged part: VeriSilicon, for example, describes its ZSP DSP IP as a series of processor cores optimised for signal processing computation and data streaming, for audio, voice, imaging, vision, wireless connectivity and power-line communications. [3]

Editorial note: the MIPS, MFLOPS and MMACS figures above are vendor peak ratings. Benchmark the actual filters, FFT sizes and frame rates of your algorithm on the candidate device or its simulator before fixing the clock grade.

Give the supplier the algorithms and sample rates (filters, FFT sizes, codecs, control loops), the number format needed (16-bit fixed, 32-bit fixed, single- or double-precision floating point), the processing budget per frame, on-chip memory required, the software tools and libraries expected, whether a packaged chip or a licensed core is wanted, and annual volume.

02

Set memory, interfaces, supply rails, package and temperature grade

The TMS320C6748 has 32 KB of L1 program RAM/cache, 32 KB of L1 data RAM/cache and 256 KB of unified L2, plus 128 KB of shared RAM, with an EDMA3 controller of 64 DMA channels. For audio it has one multichannel audio serial port (McASP) with two clock zones and 16 serial data pins supporting TDM and I2S, and two McBSPs; other interfaces include DDR2/mobile DDR, 10/100 Ethernet, USB 2.0 OTG, SATA, SPI, I2C, UART and a uPP parallel port for FPGAs and data converters. It comes in 361-ball BGA packages of 13 × 13 mm (0.65 mm pitch) or 16 × 16 mm (0.80 mm pitch). [1]

The C6748 core rail is variable: TI gives operating points of 1.0, 1.1, 1.2 and 1.3 V, with maximum clocks of 100, 200, 375 and 456 MHz respectively in the commercial grade, and I/O banks at 1.8 or 3.3 V. Its recommended power-on-hours table gives 100,000 hours for the 456 MHz grade at 0 to 90 °C or −40 to 90 °C junction temperature, and 75,000 hours for the 375 MHz grade at −40 to 105 °C, rising to 100,000 hours if operation is limited to 345 MHz. [1]

The TMS320C5535 family runs its core at 1.05 V for 50 MHz or 1.3 V for 100 MHz, with I/O at 1.8, 2.5, 2.75 or 3.3 V and three integrated LDOs. TI characterises active power at 25 °C as 0.15 mW/MHz at 1.05 V and 50 MHz and 0.22 mW/MHz at 1.3 V and 100 MHz, and standby power with the clock stopped from 0.15 to 0.44 mW depending on voltage and memory retention. It has 320 KB of zero-wait-state on-chip RAM and 128 KB of ROM, four I2S ports, USB 2.0 device, a 10-bit 4-input SAR ADC and a 144-ball 12 × 12 mm BGA package. [2]

Editorial calculation: at TI's characterised figures, the C5535 core draws about 0.15 mW/MHz × 50 MHz ≈ 7.5 mW at 1.05 V, and about 0.22 mW/MHz × 100 MHz = 22 mW at 1.3 V; doubling the clock roughly triples core power in this example, so choose the lowest operating point that meets the processing budget. These figures exclude I/O, memory and peripheral power. [2]

03

Compare a voice DSP with integrated microphone inputs

Cirrus Logic's CS48L32 shows a different packaging of DSP capacity: a programmable HaloCore DSP combined with microphone inputs for always-on voice processing. The product page lists a single 32-bit, dual-MAC, 100 MHz audio signal processor with 280 kB program memory and 768 kB data memory, FFT, LMS and FIR accelerators, up to four analog or four digital microphone inputs, two A/D converters at 99 dB SNR and −88 dB THD+N over 8–192 kHz sample rates, and two multichannel audio serial ports supporting formats up to 192 kHz and 32 bits. [4]

The page states 1.8 V and 1.2 V supplies, an operating temperature range of −40 to 85 °C, 64-ball WLCSP (0.4 mm ball array) and 64-pin QFN packages, and a 104 dB SNR mic input at 16 kHz, with low-power input modes for voice-trigger functions and support for third-party DSP programming. [4]

Editorial calculation: two MACs at 100 MHz give a peak of 200 million MACs per second, the same peak TI states for the C5535 at 100 MHz, [2] while the CS48L32's 280 kB + 768 kB = 1,048 kB of program and data memory compares with 320 KB of on-chip RAM on the C5535. The CS48L32 adds converters and microphone bias on the same die, so the comparison is for sizing, not a like-for-like part swap. [4]

04

ZSP cores licensed for system-on-chip designs

VeriSilicon, listed below, offers ZSP DSP processor cores for audio, voice, imaging, vision and wireless designs as IP to be built into your own chip, so the order is a licence plus tools rather than a reel of parts.

05

Core, memory, DMA and serial ports on the die

Both TI data sheets back the core, memory, DMA, serial-port, clock and power rows; the external memory interface appears only on the C6748 and the FFT accelerator only on the C5535.

06

Clock grade, number format, rails and package for the chosen device

Rows pair a C6748 figure with a C5535 figure where both data sheets give one, which shows the span between the two TI families; ask for a benchmark on your own algorithm rather than relying on peak MIPS.

07

Send the algorithm, interface and power data together

Paste it into your enquiry below or into an email to a maker, then replace every bracket.

Algorithms: [filters; FFT sizes; codecs; sample rates; channels]
Arithmetic: [fixed or floating point; MIPS or MMACS budget]
Memory: [on-chip RAM; external DDR or flash]
Interfaces: [I2S/TDM; Ethernet; USB; SPI; host port]
Power and package: [core and I/O rails; power budget; BGA size]
Supply: [temperature grade; volume; tools; packaged chip or licensed core]

See manufacturer records Send an enquiry through CNFX