How does an IC substrate differ from an ordinary PCB?

Substrates use finer geometry by an order of magnitude, tighter warpage and CTE control, and build-up dielectrics like ABF instead of standard prepreg. They are made in dedicated plants with semiconductor-grade cleanliness rather than conventional PCB lines.

Which package types does a substrate serve?

Wire-bond CSP and PBGA packages use BT-based substrates; flip-chip CSP and high-performance processors use ABF build-up substrates; SiP modules combine several dies and passives on one substrate with cavity or embedded options.

What should buyers qualify beyond electrical spec?

Warpage across reflow, moisture sensitivity handling, ENEPIG plating integrity for bonding, daisy-chain test coupon results, and the supplier's traceability of core and build-up material lots, since assembly yield depends on these more than on nominal impedance.

Editorial Technical Reference

IC Substrate

This page explains how IC Substrate is classified within Computer, Electronic and Optical Product Manufacturing. Technical values and manufacturer relationships are research references; confirm the current specification and supplier evidence for each order.

Technical Definition & Core Assembly

High-density laminate carrier that routes signals between a semiconductor die and the system PCB, forming the package's electrical and mechanical base.

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Representative manufacturing scene; not a photograph of a specific supplier or model.

Product Specifications

Technical details and manufacturing context for IC Substrate

Definition

An IC substrate is the fine-line interposer inside chip packages such as BGA, CSP, FC-CSP, SiP, and PBGA. Built on BT resin or ABF build-up layers, it fans out the die's micro-bump pitch to the coarser ball grid of the motherboard, integrating impedance-controlled routing, power and ground planes, and solder-mask-defined pads. Line widths reach 10-25 µm, far finer than conventional PCBs, and flatness, warpage, and coefficient-of-thermal-expansion control dominate quality. Substrate supply is a recognized bottleneck for advanced packaging capacity worldwide.

Working Principle

The die attaches by wire bonding or flip-chip bumps to the substrate's top pads; build-up layers redistribute each net through microvias and fine traces to the bottom ball pads. The substrate thus translates chip-scale geometry to board-scale geometry while managing signal integrity, power delivery, and heat spreading.

Common Materials

BT (bismaleimide triazine) resin core, ABF (Ajinomoto build-up film) layers, electro-deposited copper with ENEPIG finish, photoimageable solder mask, glass cloth reinforcement

line space:	10-25 µm typical
layer builds:	1+2+1 up to 5+2+5 and beyond
package types:	BGA, CSP, FC-CSP, SiP, PBGA
qualification:	JEDEC reliability plus IPC-6012 substrate addenda
surface finish:	ENEPIG, OSP on selective pads

IC Substrate

Product Specifications

Industry Taxonomies & Aliases

Application Fit & Sizing Matrix