This page explains how IC Substrate is classified within Computer, Electronic and Optical Product Manufacturing. Technical values and manufacturer relationships are research references; confirm the current specification and supplier evidence for each order.
High-density laminate carrier that routes signals between a semiconductor die and the system PCB, forming the package's electrical and mechanical base.
Technical details and manufacturing context for IC Substrate
| Parameter | Typical range | Notes & selection driver |
|---|---|---|
| Substrate Size (Length × Width) | 10–50 × 10–50 mm | Custom sizes available; larger sizes increase warpage risk. |
| Layer Count | 2–20 layers | Higher layer count enables more complex routing. |
| Minimum Line Width/Space | 8–15 μm | Finer geometries require advanced lithography. |
| Dielectric Constant (Dk) | 3.0–4.5 | Lower Dk improves signal speed. |
| Dissipation Factor (Df) | 0.002–0.010 | Lower Df reduces signal loss. |
| Characteristic Impedance | 50 ±10% Ω | Controlled impedance for high-speed signals. |
| Insulation Resistance | ≥1×10^9 Ω | Minimum between adjacent conductors. |
| Breakdown Voltage | ≥500 V DC | Ensures electrical isolation. |
| Operating Temperature Range | -40–125 °C | Exceeding range may cause delamination. |
| Thermal Conductivity | 0.3–1.0 W/m·K | Higher values improve heat dissipation. |
| Coefficient of Thermal Expansion (CTE) | 10–16 ppm/°C | Mismatch with die causes stress. |
| Moisture Sensitivity Level (MSL) | 1–3 | Lower MSL requires stricter handling.IPC/JEDEC J-STD-020 |
| Surface Finish | ENIG, OSP, HASL | ENIG for fine pitch; OSP for cost. |
| Weight | 0.5–5.0 g | Depends on size and layer count. |
Ranges are indicative industry figures for RFQ preparation, not a supplier commitment. Confirm every value and standard with the legal manufacturer before ordering.
| line space: | 10-25 µm typical |
| layer builds: | 1+2+1 up to 5+2+5 and beyond |
| package types: | BGA, CSP, FC-CSP, SiP, PBGA |
| qualification: | JEDEC reliability plus IPC-6012 substrate addenda |
| surface finish: | ENEPIG, OSP on selective pads |
Indicative industry ranges for design and RFQ preparation. Confirm the exact figures and applicable standard with the manufacturer before specifying.
A practical evidence checklist for RFQ preparation and supplier evaluation.
CNFX does not score or rank suppliers. Buyers must verify all claims and documents with the legal manufacturer before ordering.
10 companies list this product among what they make. Company figures are quoted from each company's own website; every card states where the relationship came from.
Manufacturer listings support early research and capability understanding. They are not certification, ranking, or transaction guarantees.
Ask for use case, specification boundaries, supplier type, and RFQ preparation information for this product.
According to the directory, the substrate size ranges from 10 to 50 mm per side. Larger sizes increase warpage risk, so confirm the specific dimensions with the manufacturer for your application.
Key parameters include characteristic impedance (50 Ω ±10%), insulation resistance (≥1×10^9 Ω), breakdown voltage (≥500 V DC), dielectric constant (3.0–4.5), and dissipation factor (0.002–0.010). These affect signal integrity and must be verified for the specific substrate.
Relevant standards include IPC-6012 with substrate addenda, JEDEC package outline standards, and IPC-TM-650 test methods. These are references for procurement and verification; compliance must be confirmed with the supplier.
Common materials include BT resin core, ABF build-up layers, electro-deposited copper with ENEPIG finish, photoimageable solder mask, and glass cloth reinforcement. Material selection affects electrical and thermal performance.
Editorial classification, named public sources where available, and source-reviewed manufacturer records.
Compare manufacturer profiles with relevant product and process capability.